Summary - Blocks of 256 instructions

x0zz x1zz x2zz x3zz x4zz x5zz x6zz x7zz x8zz x9zz xAzz xBzz xCzz xDzz xEzz xFzz
0xzz 255 [R], nop movw muls fmul, fmuls, fmulsu, mulsu cpc sbc add
1xzz cpse cp sub adc
2xzz and eor or mov
3xzz cpi
4xzz sbci
5xzz subi
6xzz ori
7xzz andi
8xzz 32 ld, 224 ldd 32 st, 224 std ldd std ldd std ldd std
9xzz (MISC) 112 [R], 16 push, 112 st, 16 sts (MISC) (MISC) adiw sbiw cbi sbic sbi sbis mul
Axzz ldd std ldd std ldd std ldd std
Bxzz in out
Cxzz rjmp
Dxzz rcall
Exzz ldi
Fxzz Conditional Branches Conditional Branches [R], bld [R], bst [R], sbrc [R], sbrs

[R] = Reserved
Yellow boxes contain some two-word instructions

Number of reserved opcodes: 1682 (2.6%)

Opcodes 00xx (0x0000 - 0x00FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
000x nop [R]
001x [R]
002x [R]
003x [R]
004x [R]
005x [R]
006x [R]
007x [R]
008x [R]
009x [R]
00Ax [R]
00Bx [R]
00Cx [R]
00Dx [R]
00Ex [R]
00Fx [R]

[R] = Reserved (255)

nop - No OPeration
^ summary

Opcodes 03xx (0x0300 - 0x03FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
030x mulsu r16, r16 mulsu r16, r17 mulsu r16, r18 mulsu r16, r19 mulsu r16, r20 mulsu r16, r21 mulsu r16, r22 mulsu r16, r23 fmul r16, r16 fmul r16, r17 fmul r16, r18 fmul r16, r19 fmul r16, r20 fmul r16, r21 fmul r16, r22 fmul r16, r23
031x mulsu r17, r16 mulsu r17, r17 mulsu r17, r18 mulsu r17, r19 mulsu r17, r20 mulsu r17, r21 mulsu r17, r22 mulsu r17, r23 fmul r17, r16 fmul r17, r17 fmul r17, r18 fmul r17, r19 fmul r17, r20 fmul r17, r21 fmul r17, r22 fmul r17, r23
032x mulsu r18, r16 mulsu r18, r17 mulsu r18, r18 mulsu r18, r19 mulsu r18, r20 mulsu r18, r21 mulsu r18, r22 mulsu r18, r23 fmul r18, r16 fmul r18, r17 fmul r18, r18 fmul r18, r19 fmul r18, r20 fmul r18, r21 fmul r18, r22 fmul r18, r23
033x mulsu r19, r16 mulsu r19, r17 mulsu r19, r18 mulsu r19, r19 mulsu r19, r20 mulsu r19, r21 mulsu r19, r22 mulsu r19, r23 fmul r19, r16 fmul r19, r17 fmul r19, r18 fmul r19, r19 fmul r19, r20 fmul r19, r21 fmul r19, r22 fmul r19, r23
034x mulsu r20, r16 mulsu r20, r17 mulsu r20, r18 mulsu r20, r19 mulsu r20, r20 mulsu r20, r21 mulsu r20, r22 mulsu r20, r23 fmul r20, r16 fmul r20, r17 fmul r20, r18 fmul r20, r19 fmul r20, r20 fmul r20, r21 fmul r20, r22 fmul r20, r23
035x mulsu r21, r16 mulsu r21, r17 mulsu r21, r18 mulsu r21, r19 mulsu r21, r20 mulsu r21, r21 mulsu r21, r22 mulsu r21, r23 fmul r21, r16 fmul r21, r17 fmul r21, r18 fmul r21, r19 fmul r21, r20 fmul r21, r21 fmul r21, r22 fmul r21, r23
036x mulsu r22, r16 mulsu r22, r17 mulsu r22, r18 mulsu r22, r19 mulsu r22, r20 mulsu r22, r21 mulsu r22, r22 mulsu r22, r23 fmul r22, r16 fmul r22, r17 fmul r22, r18 fmul r22, r19 fmul r22, r20 fmul r22, r21 fmul r22, r22 fmul r22, r23
037x mulsu r23, r16 mulsu r23, r17 mulsu r23, r18 mulsu r23, r19 mulsu r23, r20 mulsu r23, r21 mulsu r23, r22 mulsu r23, r23 fmul r23, r16 fmul r23, r17 fmul r23, r18 fmul r23, r19 fmul r23, r20 fmul r23, r21 fmul r23, r22 fmul r23, r23
038x fmuls r16, r16 fmuls r16, r17 fmuls r16, r18 fmuls r16, r19 fmuls r16, r20 fmuls r16, r21 fmuls r16, r22 fmuls r16, r23 fmulsu r16, r16 fmulsu r16, r17 fmulsu r16, r18 fmulsu r16, r19 fmulsu r16, r20 fmulsu r16, r21 fmulsu r16, r22 fmulsu r16, r23
039x fmuls r17, r16 fmuls r17, r17 fmuls r17, r18 fmuls r17, r19 fmuls r17, r20 fmuls r17, r21 fmuls r17, r22 fmuls r17, r23 fmulsu r17, r16 fmulsu r17, r17 fmulsu r17, r18 fmulsu r17, r19 fmulsu r17, r20 fmulsu r17, r21 fmulsu r17, r22 fmulsu r17, r23
03Ax fmuls r18, r16 fmuls r18, r17 fmuls r18, r18 fmuls r18, r19 fmuls r18, r20 fmuls r18, r21 fmuls r18, r22 fmuls r18, r23 fmulsu r18, r16 fmulsu r18, r17 fmulsu r18, r18 fmulsu r18, r19 fmulsu r18, r20 fmulsu r18, r21 fmulsu r18, r22 fmulsu r18, r23
03Bx fmuls r19, r16 fmuls r19, r17 fmuls r19, r18 fmuls r19, r19 fmuls r19, r20 fmuls r19, r21 fmuls r19, r22 fmuls r19, r23 fmulsu r19, r16 fmulsu r19, r17 fmulsu r19, r18 fmulsu r19, r19 fmulsu r19, r20 fmulsu r19, r21 fmulsu r19, r22 fmulsu r19, r23
03Cx fmuls r20, r16 fmuls r20, r17 fmuls r20, r18 fmuls r20, r19 fmuls r20, r20 fmuls r20, r21 fmuls r20, r22 fmuls r20, r23 fmulsu r20, r16 fmulsu r20, r17 fmulsu r20, r18 fmulsu r20, r19 fmulsu r20, r20 fmulsu r20, r21 fmulsu r20, r22 fmulsu r20, r23
03Dx fmuls r21, r16 fmuls r21, r17 fmuls r21, r18 fmuls r21, r19 fmuls r21, r20 fmuls r21, r21 fmuls r21, r22 fmuls r21, r23 fmulsu r21, r16 fmulsu r21, r17 fmulsu r21, r18 fmulsu r21, r19 fmulsu r21, r20 fmulsu r21, r21 fmulsu r21, r22 fmulsu r21, r23
03Ex fmuls r22, r16 fmuls r22, r17 fmuls r22, r18 fmuls r22, r19 fmuls r22, r20 fmuls r22, r21 fmuls r22, r22 fmuls r22, r23 fmulsu r22, r16 fmulsu r22, r17 fmulsu r22, r18 fmulsu r22, r19 fmulsu r22, r20 fmulsu r22, r21 fmulsu r22, r22 fmulsu r22, r23
03Fx fmuls r23, r16 fmuls r23, r17 fmuls r23, r18 fmuls r23, r19 fmuls r23, r20 fmuls r23, r21 fmuls r23, r22 fmuls r23, r23 fmulsu r23, r16 fmulsu r23, r17 fmulsu r23, r18 fmulsu r23, r19 fmulsu r23, r20 fmulsu r23, r21 fmulsu r23, r22 fmulsu r23, r23
fmul - Fractional MULtiply unsigned (from two registers, into R1:R0)
fmuls - Fractional MULtiply Signed (from two registers, into R1:R0)
fmulsu - Fractional MULtiply Signed with Unsigned (from two registers, into R1:R0)
mulsu - MULtiply Signed by Unsigned (from two registers, into R1:R0)
^ summary

Opcodes 80xx (0x8000 - 0x80FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
800x ld r0, Z ldd r0, Z+1 ldd r0, Z+2 ldd r0, Z+3 ldd r0, Z+4 ldd r0, Z+5 ldd r0, Z+6 ldd r0, Z+7 ld r0, Y ldd r0, Y+1 ldd r0, Y+2 ldd r0, Y+3 ldd r0, Y+4 ldd r0, Y+5 ldd r0, Y+6 ldd r0, Y+7
801x ld r1, Z ldd r1, Z+1 ldd r1, Z+2 ldd r1, Z+3 ldd r1, Z+4 ldd r1, Z+5 ldd r1, Z+6 ldd r1, Z+7 ld r1, Y ldd r1, Y+1 ldd r1, Y+2 ldd r1, Y+3 ldd r1, Y+4 ldd r1, Y+5 ldd r1, Y+6 ldd r1, Y+7
802x ld r2, Z ldd r2, Z+1 ldd r2, Z+2 ldd r2, Z+3 ldd r2, Z+4 ldd r2, Z+5 ldd r2, Z+6 ldd r2, Z+7 ld r2, Y ldd r2, Y+1 ldd r2, Y+2 ldd r2, Y+3 ldd r2, Y+4 ldd r2, Y+5 ldd r2, Y+6 ldd r2, Y+7
803x ld r3, Z ldd r3, Z+1 ldd r3, Z+2 ldd r3, Z+3 ldd r3, Z+4 ldd r3, Z+5 ldd r3, Z+6 ldd r3, Z+7 ld r3, Y ldd r3, Y+1 ldd r3, Y+2 ldd r3, Y+3 ldd r3, Y+4 ldd r3, Y+5 ldd r3, Y+6 ldd r3, Y+7
804x ld r4, Z ldd r4, Z+1 ldd r4, Z+2 ldd r4, Z+3 ldd r4, Z+4 ldd r4, Z+5 ldd r4, Z+6 ldd r4, Z+7 ld r4, Y ldd r4, Y+1 ldd r4, Y+2 ldd r4, Y+3 ldd r4, Y+4 ldd r4, Y+5 ldd r4, Y+6 ldd r4, Y+7
805x ld r5, Z ldd r5, Z+1 ldd r5, Z+2 ldd r5, Z+3 ldd r5, Z+4 ldd r5, Z+5 ldd r5, Z+6 ldd r5, Z+7 ld r5, Y ldd r5, Y+1 ldd r5, Y+2 ldd r5, Y+3 ldd r5, Y+4 ldd r5, Y+5 ldd r5, Y+6 ldd r5, Y+7
806x ld r6, Z ldd r6, Z+1 ldd r6, Z+2 ldd r6, Z+3 ldd r6, Z+4 ldd r6, Z+5 ldd r6, Z+6 ldd r6, Z+7 ld r6, Y ldd r6, Y+1 ldd r6, Y+2 ldd r6, Y+3 ldd r6, Y+4 ldd r6, Y+5 ldd r6, Y+6 ldd r6, Y+7
807x ld r7, Z ldd r7, Z+1 ldd r7, Z+2 ldd r7, Z+3 ldd r7, Z+4 ldd r7, Z+5 ldd r7, Z+6 ldd r7, Z+7 ld r7, Y ldd r7, Y+1 ldd r7, Y+2 ldd r7, Y+3 ldd r7, Y+4 ldd r7, Y+5 ldd r7, Y+6 ldd r7, Y+7
808x ld r8, Z ldd r8, Z+1 ldd r8, Z+2 ldd r8, Z+3 ldd r8, Z+4 ldd r8, Z+5 ldd r8, Z+6 ldd r8, Z+7 ld r8, Y ldd r8, Y+1 ldd r8, Y+2 ldd r8, Y+3 ldd r8, Y+4 ldd r8, Y+5 ldd r8, Y+6 ldd r8, Y+7
809x ld r9, Z ldd r9, Z+1 ldd r9, Z+2 ldd r9, Z+3 ldd r9, Z+4 ldd r9, Z+5 ldd r9, Z+6 ldd r9, Z+7 ld r9, Y ldd r9, Y+1 ldd r9, Y+2 ldd r9, Y+3 ldd r9, Y+4 ldd r9, Y+5 ldd r9, Y+6 ldd r9, Y+7
80Ax ld r10, Z ldd r10, Z+1 ldd r10, Z+2 ldd r10, Z+3 ldd r10, Z+4 ldd r10, Z+5 ldd r10, Z+6 ldd r10, Z+7 ld r10, Y ldd r10, Y+1 ldd r10, Y+2 ldd r10, Y+3 ldd r10, Y+4 ldd r10, Y+5 ldd r10, Y+6 ldd r10, Y+7
80Bx ld r11, Z ldd r11, Z+1 ldd r11, Z+2 ldd r11, Z+3 ldd r11, Z+4 ldd r11, Z+5 ldd r11, Z+6 ldd r11, Z+7 ld r11, Y ldd r11, Y+1 ldd r11, Y+2 ldd r11, Y+3 ldd r11, Y+4 ldd r11, Y+5 ldd r11, Y+6 ldd r11, Y+7
80Cx ld r12, Z ldd r12, Z+1 ldd r12, Z+2 ldd r12, Z+3 ldd r12, Z+4 ldd r12, Z+5 ldd r12, Z+6 ldd r12, Z+7 ld r12, Y ldd r12, Y+1 ldd r12, Y+2 ldd r12, Y+3 ldd r12, Y+4 ldd r12, Y+5 ldd r12, Y+6 ldd r12, Y+7
80Dx ld r13, Z ldd r13, Z+1 ldd r13, Z+2 ldd r13, Z+3 ldd r13, Z+4 ldd r13, Z+5 ldd r13, Z+6 ldd r13, Z+7 ld r13, Y ldd r13, Y+1 ldd r13, Y+2 ldd r13, Y+3 ldd r13, Y+4 ldd r13, Y+5 ldd r13, Y+6 ldd r13, Y+7
80Ex ld r14, Z ldd r14, Z+1 ldd r14, Z+2 ldd r14, Z+3 ldd r14, Z+4 ldd r14, Z+5 ldd r14, Z+6 ldd r14, Z+7 ld r14, Y ldd r14, Y+1 ldd r14, Y+2 ldd r14, Y+3 ldd r14, Y+4 ldd r14, Y+5 ldd r14, Y+6 ldd r14, Y+7
80Fx ld r15, Z ldd r15, Z+1 ldd r15, Z+2 ldd r15, Z+3 ldd r15, Z+4 ldd r15, Z+5 ldd r15, Z+6 ldd r15, Z+7 ld r15, Y ldd r15, Y+1 ldd r15, Y+2 ldd r15, Y+3 ldd r15, Y+4 ldd r15, Y+5 ldd r15, Y+6 ldd r15, Y+7
ld - LoaD register indirect from data space
ldd - LoaD register indirect from data space with Displacement
^ summary

Opcodes 81xx (0x8100 - 0x81FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
810x ld r16, Z ldd r16, Z+1 ldd r16, Z+2 ldd r16, Z+3 ldd r16, Z+4 ldd r16, Z+5 ldd r16, Z+6 ldd r16, Z+7 ld r16, Y ldd r16, Y+1 ldd r16, Y+2 ldd r16, Y+3 ldd r16, Y+4 ldd r16, Y+5 ldd r16, Y+6 ldd r16, Y+7
811x ld r17, Z ldd r17, Z+1 ldd r17, Z+2 ldd r17, Z+3 ldd r17, Z+4 ldd r17, Z+5 ldd r17, Z+6 ldd r17, Z+7 ld r17, Y ldd r17, Y+1 ldd r17, Y+2 ldd r17, Y+3 ldd r17, Y+4 ldd r17, Y+5 ldd r17, Y+6 ldd r17, Y+7
812x ld r18, Z ldd r18, Z+1 ldd r18, Z+2 ldd r18, Z+3 ldd r18, Z+4 ldd r18, Z+5 ldd r18, Z+6 ldd r18, Z+7 ld r18, Y ldd r18, Y+1 ldd r18, Y+2 ldd r18, Y+3 ldd r18, Y+4 ldd r18, Y+5 ldd r18, Y+6 ldd r18, Y+7
813x ld r19, Z ldd r19, Z+1 ldd r19, Z+2 ldd r19, Z+3 ldd r19, Z+4 ldd r19, Z+5 ldd r19, Z+6 ldd r19, Z+7 ld r19, Y ldd r19, Y+1 ldd r19, Y+2 ldd r19, Y+3 ldd r19, Y+4 ldd r19, Y+5 ldd r19, Y+6 ldd r19, Y+7
814x ld r20, Z ldd r20, Z+1 ldd r20, Z+2 ldd r20, Z+3 ldd r20, Z+4 ldd r20, Z+5 ldd r20, Z+6 ldd r20, Z+7 ld r20, Y ldd r20, Y+1 ldd r20, Y+2 ldd r20, Y+3 ldd r20, Y+4 ldd r20, Y+5 ldd r20, Y+6 ldd r20, Y+7
815x ld r21, Z ldd r21, Z+1 ldd r21, Z+2 ldd r21, Z+3 ldd r21, Z+4 ldd r21, Z+5 ldd r21, Z+6 ldd r21, Z+7 ld r21, Y ldd r21, Y+1 ldd r21, Y+2 ldd r21, Y+3 ldd r21, Y+4 ldd r21, Y+5 ldd r21, Y+6 ldd r21, Y+7
816x ld r22, Z ldd r22, Z+1 ldd r22, Z+2 ldd r22, Z+3 ldd r22, Z+4 ldd r22, Z+5 ldd r22, Z+6 ldd r22, Z+7 ld r22, Y ldd r22, Y+1 ldd r22, Y+2 ldd r22, Y+3 ldd r22, Y+4 ldd r22, Y+5 ldd r22, Y+6 ldd r22, Y+7
817x ld r23, Z ldd r23, Z+1 ldd r23, Z+2 ldd r23, Z+3 ldd r23, Z+4 ldd r23, Z+5 ldd r23, Z+6 ldd r23, Z+7 ld r23, Y ldd r23, Y+1 ldd r23, Y+2 ldd r23, Y+3 ldd r23, Y+4 ldd r23, Y+5 ldd r23, Y+6 ldd r23, Y+7
818x ld r24, Z ldd r24, Z+1 ldd r24, Z+2 ldd r24, Z+3 ldd r24, Z+4 ldd r24, Z+5 ldd r24, Z+6 ldd r24, Z+7 ld r24, Y ldd r24, Y+1 ldd r24, Y+2 ldd r24, Y+3 ldd r24, Y+4 ldd r24, Y+5 ldd r24, Y+6 ldd r24, Y+7
819x ld r25, Z ldd r25, Z+1 ldd r25, Z+2 ldd r25, Z+3 ldd r25, Z+4 ldd r25, Z+5 ldd r25, Z+6 ldd r25, Z+7 ld r25, Y ldd r25, Y+1 ldd r25, Y+2 ldd r25, Y+3 ldd r25, Y+4 ldd r25, Y+5 ldd r25, Y+6 ldd r25, Y+7
81Ax ld r26, Z ldd r26, Z+1 ldd r26, Z+2 ldd r26, Z+3 ldd r26, Z+4 ldd r26, Z+5 ldd r26, Z+6 ldd r26, Z+7 ld r26, Y ldd r26, Y+1 ldd r26, Y+2 ldd r26, Y+3 ldd r26, Y+4 ldd r26, Y+5 ldd r26, Y+6 ldd r26, Y+7
81Bx ld r27, Z ldd r27, Z+1 ldd r27, Z+2 ldd r27, Z+3 ldd r27, Z+4 ldd r27, Z+5 ldd r27, Z+6 ldd r27, Z+7 ld r27, Y ldd r27, Y+1 ldd r27, Y+2 ldd r27, Y+3 ldd r27, Y+4 ldd r27, Y+5 ldd r27, Y+6 ldd r27, Y+7
81Cx ld r28, Z ldd r28, Z+1 ldd r28, Z+2 ldd r28, Z+3 ldd r28, Z+4 ldd r28, Z+5 ldd r28, Z+6 ldd r28, Z+7 ld r28, Y ldd r28, Y+1 ldd r28, Y+2 ldd r28, Y+3 ldd r28, Y+4 ldd r28, Y+5 ldd r28, Y+6 ldd r28, Y+7
81Dx ld r29, Z ldd r29, Z+1 ldd r29, Z+2 ldd r29, Z+3 ldd r29, Z+4 ldd r29, Z+5 ldd r29, Z+6 ldd r29, Z+7 ld r29, Y ldd r29, Y+1 ldd r29, Y+2 ldd r29, Y+3 ldd r29, Y+4 ldd r29, Y+5 ldd r29, Y+6 ldd r29, Y+7
81Ex ld r30, Z ldd r30, Z+1 ldd r30, Z+2 ldd r30, Z+3 ldd r30, Z+4 ldd r30, Z+5 ldd r30, Z+6 ldd r30, Z+7 ld r30, Y ldd r30, Y+1 ldd r30, Y+2 ldd r30, Y+3 ldd r30, Y+4 ldd r30, Y+5 ldd r30, Y+6 ldd r30, Y+7
81Fx ld r31, Z ldd r31, Z+1 ldd r31, Z+2 ldd r31, Z+3 ldd r31, Z+4 ldd r31, Z+5 ldd r31, Z+6 ldd r31, Z+7 ld r31, Y ldd r31, Y+1 ldd r31, Y+2 ldd r31, Y+3 ldd r31, Y+4 ldd r31, Y+5 ldd r31, Y+6 ldd r31, Y+7
ld - LoaD register indirect from data space
ldd - LoaD register indirect from data space with Displacement
^ summary

Opcodes 82xx (0x8200 - 0x82FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
820x st Z, r0 std Z+1, r0 std Z+2, r0 std Z+3, r0 std Z+4, r0 std Z+5, r0 std Z+6, r0 std Z+7, r0 st Y, r0 std Y+1, r0 std Y+2, r0 std Y+3, r0 std Y+4, r0 std Y+5, r0 std Y+6, r0 std Y+7, r0
821x st Z, r1 std Z+1, r1 std Z+2, r1 std Z+3, r1 std Z+4, r1 std Z+5, r1 std Z+6, r1 std Z+7, r1 st Y, r1 std Y+1, r1 std Y+2, r1 std Y+3, r1 std Y+4, r1 std Y+5, r1 std Y+6, r1 std Y+7, r1
822x st Z, r2 std Z+1, r2 std Z+2, r2 std Z+3, r2 std Z+4, r2 std Z+5, r2 std Z+6, r2 std Z+7, r2 st Y, r2 std Y+1, r2 std Y+2, r2 std Y+3, r2 std Y+4, r2 std Y+5, r2 std Y+6, r2 std Y+7, r2
823x st Z, r3 std Z+1, r3 std Z+2, r3 std Z+3, r3 std Z+4, r3 std Z+5, r3 std Z+6, r3 std Z+7, r3 st Y, r3 std Y+1, r3 std Y+2, r3 std Y+3, r3 std Y+4, r3 std Y+5, r3 std Y+6, r3 std Y+7, r3
824x st Z, r4 std Z+1, r4 std Z+2, r4 std Z+3, r4 std Z+4, r4 std Z+5, r4 std Z+6, r4 std Z+7, r4 st Y, r4 std Y+1, r4 std Y+2, r4 std Y+3, r4 std Y+4, r4 std Y+5, r4 std Y+6, r4 std Y+7, r4
825x st Z, r5 std Z+1, r5 std Z+2, r5 std Z+3, r5 std Z+4, r5 std Z+5, r5 std Z+6, r5 std Z+7, r5 st Y, r5 std Y+1, r5 std Y+2, r5 std Y+3, r5 std Y+4, r5 std Y+5, r5 std Y+6, r5 std Y+7, r5
826x st Z, r6 std Z+1, r6 std Z+2, r6 std Z+3, r6 std Z+4, r6 std Z+5, r6 std Z+6, r6 std Z+7, r6 st Y, r6 std Y+1, r6 std Y+2, r6 std Y+3, r6 std Y+4, r6 std Y+5, r6 std Y+6, r6 std Y+7, r6
827x st Z, r7 std Z+1, r7 std Z+2, r7 std Z+3, r7 std Z+4, r7 std Z+5, r7 std Z+6, r7 std Z+7, r7 st Y, r7 std Y+1, r7 std Y+2, r7 std Y+3, r7 std Y+4, r7 std Y+5, r7 std Y+6, r7 std Y+7, r7
828x st Z, r8 std Z+1, r8 std Z+2, r8 std Z+3, r8 std Z+4, r8 std Z+5, r8 std Z+6, r8 std Z+7, r8 st Y, r8 std Y+1, r8 std Y+2, r8 std Y+3, r8 std Y+4, r8 std Y+5, r8 std Y+6, r8 std Y+7, r8
829x st Z, r9 std Z+1, r9 std Z+2, r9 std Z+3, r9 std Z+4, r9 std Z+5, r9 std Z+6, r9 std Z+7, r9 st Y, r9 std Y+1, r9 std Y+2, r9 std Y+3, r9 std Y+4, r9 std Y+5, r9 std Y+6, r9 std Y+7, r9
82Ax st Z, r10 std Z+1, r10 std Z+2, r10 std Z+3, r10 std Z+4, r10 std Z+5, r10 std Z+6, r10 std Z+7, r10 st Y, r10 std Y+1, r10 std Y+2, r10 std Y+3, r10 std Y+4, r10 std Y+5, r10 std Y+6, r10 std Y+7, r10
82Bx st Z, r11 std Z+1, r11 std Z+2, r11 std Z+3, r11 std Z+4, r11 std Z+5, r11 std Z+6, r11 std Z+7, r11 st Y, r11 std Y+1, r11 std Y+2, r11 std Y+3, r11 std Y+4, r11 std Y+5, r11 std Y+6, r11 std Y+7, r11
82Cx st Z, r12 std Z+1, r12 std Z+2, r12 std Z+3, r12 std Z+4, r12 std Z+5, r12 std Z+6, r12 std Z+7, r12 st Y, r12 std Y+1, r12 std Y+2, r12 std Y+3, r12 std Y+4, r12 std Y+5, r12 std Y+6, r12 std Y+7, r12
82Dx st Z, r13 std Z+1, r13 std Z+2, r13 std Z+3, r13 std Z+4, r13 std Z+5, r13 std Z+6, r13 std Z+7, r13 st Y, r13 std Y+1, r13 std Y+2, r13 std Y+3, r13 std Y+4, r13 std Y+5, r13 std Y+6, r13 std Y+7, r13
82Ex st Z, r14 std Z+1, r14 std Z+2, r14 std Z+3, r14 std Z+4, r14 std Z+5, r14 std Z+6, r14 std Z+7, r14 st Y, r14 std Y+1, r14 std Y+2, r14 std Y+3, r14 std Y+4, r14 std Y+5, r14 std Y+6, r14 std Y+7, r14
82Fx st Z, r15 std Z+1, r15 std Z+2, r15 std Z+3, r15 std Z+4, r15 std Z+5, r15 std Z+6, r15 std Z+7, r15 st Y, r15 std Y+1, r15 std Y+2, r15 std Y+3, r15 std Y+4, r15 std Y+5, r15 std Y+6, r15 std Y+7, r15
st - STore
std - STore with Displacement
^ summary

Opcodes 83xx (0x8300 - 0x83FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
830x st Z, r16 std Z+1, r16 std Z+2, r16 std Z+3, r16 std Z+4, r16 std Z+5, r16 std Z+6, r16 std Z+7, r16 st Y, r16 std Y+1, r16 std Y+2, r16 std Y+3, r16 std Y+4, r16 std Y+5, r16 std Y+6, r16 std Y+7, r16
831x st Z, r17 std Z+1, r17 std Z+2, r17 std Z+3, r17 std Z+4, r17 std Z+5, r17 std Z+6, r17 std Z+7, r17 st Y, r17 std Y+1, r17 std Y+2, r17 std Y+3, r17 std Y+4, r17 std Y+5, r17 std Y+6, r17 std Y+7, r17
832x st Z, r18 std Z+1, r18 std Z+2, r18 std Z+3, r18 std Z+4, r18 std Z+5, r18 std Z+6, r18 std Z+7, r18 st Y, r18 std Y+1, r18 std Y+2, r18 std Y+3, r18 std Y+4, r18 std Y+5, r18 std Y+6, r18 std Y+7, r18
833x st Z, r19 std Z+1, r19 std Z+2, r19 std Z+3, r19 std Z+4, r19 std Z+5, r19 std Z+6, r19 std Z+7, r19 st Y, r19 std Y+1, r19 std Y+2, r19 std Y+3, r19 std Y+4, r19 std Y+5, r19 std Y+6, r19 std Y+7, r19
834x st Z, r20 std Z+1, r20 std Z+2, r20 std Z+3, r20 std Z+4, r20 std Z+5, r20 std Z+6, r20 std Z+7, r20 st Y, r20 std Y+1, r20 std Y+2, r20 std Y+3, r20 std Y+4, r20 std Y+5, r20 std Y+6, r20 std Y+7, r20
835x st Z, r21 std Z+1, r21 std Z+2, r21 std Z+3, r21 std Z+4, r21 std Z+5, r21 std Z+6, r21 std Z+7, r21 st Y, r21 std Y+1, r21 std Y+2, r21 std Y+3, r21 std Y+4, r21 std Y+5, r21 std Y+6, r21 std Y+7, r21
836x st Z, r22 std Z+1, r22 std Z+2, r22 std Z+3, r22 std Z+4, r22 std Z+5, r22 std Z+6, r22 std Z+7, r22 st Y, r22 std Y+1, r22 std Y+2, r22 std Y+3, r22 std Y+4, r22 std Y+5, r22 std Y+6, r22 std Y+7, r22
837x st Z, r23 std Z+1, r23 std Z+2, r23 std Z+3, r23 std Z+4, r23 std Z+5, r23 std Z+6, r23 std Z+7, r23 st Y, r23 std Y+1, r23 std Y+2, r23 std Y+3, r23 std Y+4, r23 std Y+5, r23 std Y+6, r23 std Y+7, r23
838x st Z, r24 std Z+1, r24 std Z+2, r24 std Z+3, r24 std Z+4, r24 std Z+5, r24 std Z+6, r24 std Z+7, r24 st Y, r24 std Y+1, r24 std Y+2, r24 std Y+3, r24 std Y+4, r24 std Y+5, r24 std Y+6, r24 std Y+7, r24
839x st Z, r25 std Z+1, r25 std Z+2, r25 std Z+3, r25 std Z+4, r25 std Z+5, r25 std Z+6, r25 std Z+7, r25 st Y, r25 std Y+1, r25 std Y+2, r25 std Y+3, r25 std Y+4, r25 std Y+5, r25 std Y+6, r25 std Y+7, r25
83Ax st Z, r26 std Z+1, r26 std Z+2, r26 std Z+3, r26 std Z+4, r26 std Z+5, r26 std Z+6, r26 std Z+7, r26 st Y, r26 std Y+1, r26 std Y+2, r26 std Y+3, r26 std Y+4, r26 std Y+5, r26 std Y+6, r26 std Y+7, r26
83Bx st Z, r27 std Z+1, r27 std Z+2, r27 std Z+3, r27 std Z+4, r27 std Z+5, r27 std Z+6, r27 std Z+7, r27 st Y, r27 std Y+1, r27 std Y+2, r27 std Y+3, r27 std Y+4, r27 std Y+5, r27 std Y+6, r27 std Y+7, r27
83Cx st Z, r28 std Z+1, r28 std Z+2, r28 std Z+3, r28 std Z+4, r28 std Z+5, r28 std Z+6, r28 std Z+7, r28 st Y, r28 std Y+1, r28 std Y+2, r28 std Y+3, r28 std Y+4, r28 std Y+5, r28 std Y+6, r28 std Y+7, r28
83Dx st Z, r29 std Z+1, r29 std Z+2, r29 std Z+3, r29 std Z+4, r29 std Z+5, r29 std Z+6, r29 std Z+7, r29 st Y, r29 std Y+1, r29 std Y+2, r29 std Y+3, r29 std Y+4, r29 std Y+5, r29 std Y+6, r29 std Y+7, r29
83Ex st Z, r30 std Z+1, r30 std Z+2, r30 std Z+3, r30 std Z+4, r30 std Z+5, r30 std Z+6, r30 std Z+7, r30 st Y, r30 std Y+1, r30 std Y+2, r30 std Y+3, r30 std Y+4, r30 std Y+5, r30 std Y+6, r30 std Y+7, r30
83Fx st Z, r31 std Z+1, r31 std Z+2, r31 std Z+3, r31 std Z+4, r31 std Z+5, r31 std Z+6, r31 std Z+7, r31 st Y, r31 std Y+1, r31 std Y+2, r31 std Y+3, r31 std Y+4, r31 std Y+5, r31 std Y+6, r31 std Y+7, r31
st - STore
std - STore with Displacement
^ summary

Opcodes 90xx (0x9000 - 0x90FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
900x lds r0, 0x9000 ld r0, Z+ ld r0, -Z [R] lpm r0, Z lpm r0, Z+ elpm r0, Z elpm r0, Z+ [R] ld r0, Y+ ld r0, -Y [R] ld r0, X ld r0, X+ ld r0, -X pop r0
901x lds r1, 0x9010 ld r1, Z+ ld r1, -Z [R] lpm r1, Z lpm r1, Z+ elpm r1, Z elpm r1, Z+ [R] ld r1, Y+ ld r1, -Y [R] ld r1, X ld r1, X+ ld r1, -X pop r1
902x lds r2, 0x9020 ld r2, Z+ ld r2, -Z [R] lpm r2, Z lpm r2, Z+ elpm r2, Z elpm r2, Z+ [R] ld r2, Y+ ld r2, -Y [R] ld r2, X ld r2, X+ ld r2, -X pop r2
903x lds r3, 0x9030 ld r3, Z+ ld r3, -Z [R] lpm r3, Z lpm r3, Z+ elpm r3, Z elpm r3, Z+ [R] ld r3, Y+ ld r3, -Y [R] ld r3, X ld r3, X+ ld r3, -X pop r3
904x lds r4, 0x9040 ld r4, Z+ ld r4, -Z [R] lpm r4, Z lpm r4, Z+ elpm r4, Z elpm r4, Z+ [R] ld r4, Y+ ld r4, -Y [R] ld r4, X ld r4, X+ ld r4, -X pop r4
905x lds r5, 0x9050 ld r5, Z+ ld r5, -Z [R] lpm r5, Z lpm r5, Z+ elpm r5, Z elpm r5, Z+ [R] ld r5, Y+ ld r5, -Y [R] ld r5, X ld r5, X+ ld r5, -X pop r5
906x lds r6, 0x9060 ld r6, Z+ ld r6, -Z [R] lpm r6, Z lpm r6, Z+ elpm r6, Z elpm r6, Z+ [R] ld r6, Y+ ld r6, -Y [R] ld r6, X ld r6, X+ ld r6, -X pop r6
907x lds r7, 0x9070 ld r7, Z+ ld r7, -Z [R] lpm r7, Z lpm r7, Z+ elpm r7, Z elpm r7, Z+ [R] ld r7, Y+ ld r7, -Y [R] ld r7, X ld r7, X+ ld r7, -X pop r7
908x lds r8, 0x9080 ld r8, Z+ ld r8, -Z [R] lpm r8, Z lpm r8, Z+ elpm r8, Z elpm r8, Z+ [R] ld r8, Y+ ld r8, -Y [R] ld r8, X ld r8, X+ ld r8, -X pop r8
909x lds r9, 0x9090 ld r9, Z+ ld r9, -Z [R] lpm r9, Z lpm r9, Z+ elpm r9, Z elpm r9, Z+ [R] ld r9, Y+ ld r9, -Y [R] ld r9, X ld r9, X+ ld r9, -X pop r9
90Ax lds r10, 0x90A0 ld r10, Z+ ld r10, -Z [R] lpm r10, Z lpm r10, Z+ elpm r10, Z elpm r10, Z+ [R] ld r10, Y+ ld r10, -Y [R] ld r10, X ld r10, X+ ld r10, -X pop r10
90Bx lds r11, 0x90B0 ld r11, Z+ ld r11, -Z [R] lpm r11, Z lpm r11, Z+ elpm r11, Z elpm r11, Z+ [R] ld r11, Y+ ld r11, -Y [R] ld r11, X ld r11, X+ ld r11, -X pop r11
90Cx lds r12, 0x90C0 ld r12, Z+ ld r12, -Z [R] lpm r12, Z lpm r12, Z+ elpm r12, Z elpm r12, Z+ [R] ld r12, Y+ ld r12, -Y [R] ld r12, X ld r12, X+ ld r12, -X pop r12
90Dx lds r13, 0x90D0 ld r13, Z+ ld r13, -Z [R] lpm r13, Z lpm r13, Z+ elpm r13, Z elpm r13, Z+ [R] ld r13, Y+ ld r13, -Y [R] ld r13, X ld r13, X+ ld r13, -X pop r13
90Ex lds r14, 0x90E0 ld r14, Z+ ld r14, -Z [R] lpm r14, Z lpm r14, Z+ elpm r14, Z elpm r14, Z+ [R] ld r14, Y+ ld r14, -Y [R] ld r14, X ld r14, X+ ld r14, -X pop r14
90Fx lds r15, 0x90F0 ld r15, Z+ ld r15, -Z [R] lpm r15, Z lpm r15, Z+ elpm r15, Z elpm r15, Z+ [R] ld r15, Y+ ld r15, -Y [R] ld r15, X ld r15, X+ ld r15, -X pop r15

Yellow = two-word instruction (16)
[R] = Reserved (48)

elpm - Extended Load from Program Memory (from RAMPZ + Z)
ld - LoaD register indirect from data space
lds - Load register direct from Data Space
lpm - Load register from Program Memory (from Z)
pop - POP one byte from stack into the register
^ summary

Opcodes 91xx (0x9100 - 0x91FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
910x lds r16, 0x9100 ld r16, Z+ ld r16, -Z [R] lpm r16, Z lpm r16, Z+ elpm r16, Z elpm r16, Z+ [R] ld r16, Y+ ld r16, -Y [R] ld r16, X ld r16, X+ ld r16, -X pop r16
911x lds r17, 0x9110 ld r17, Z+ ld r17, -Z [R] lpm r17, Z lpm r17, Z+ elpm r17, Z elpm r17, Z+ [R] ld r17, Y+ ld r17, -Y [R] ld r17, X ld r17, X+ ld r17, -X pop r17
912x lds r18, 0x9120 ld r18, Z+ ld r18, -Z [R] lpm r18, Z lpm r18, Z+ elpm r18, Z elpm r18, Z+ [R] ld r18, Y+ ld r18, -Y [R] ld r18, X ld r18, X+ ld r18, -X pop r18
913x lds r19, 0x9130 ld r19, Z+ ld r19, -Z [R] lpm r19, Z lpm r19, Z+ elpm r19, Z elpm r19, Z+ [R] ld r19, Y+ ld r19, -Y [R] ld r19, X ld r19, X+ ld r19, -X pop r19
914x lds r20, 0x9140 ld r20, Z+ ld r20, -Z [R] lpm r20, Z lpm r20, Z+ elpm r20, Z elpm r20, Z+ [R] ld r20, Y+ ld r20, -Y [R] ld r20, X ld r20, X+ ld r20, -X pop r20
915x lds r21, 0x9150 ld r21, Z+ ld r21, -Z [R] lpm r21, Z lpm r21, Z+ elpm r21, Z elpm r21, Z+ [R] ld r21, Y+ ld r21, -Y [R] ld r21, X ld r21, X+ ld r21, -X pop r21
916x lds r22, 0x9160 ld r22, Z+ ld r22, -Z [R] lpm r22, Z lpm r22, Z+ elpm r22, Z elpm r22, Z+ [R] ld r22, Y+ ld r22, -Y [R] ld r22, X ld r22, X+ ld r22, -X pop r22
917x lds r23, 0x9170 ld r23, Z+ ld r23, -Z [R] lpm r23, Z lpm r23, Z+ elpm r23, Z elpm r23, Z+ [R] ld r23, Y+ ld r23, -Y [R] ld r23, X ld r23, X+ ld r23, -X pop r23
918x lds r24, 0x9180 ld r24, Z+ ld r24, -Z [R] lpm r24, Z lpm r24, Z+ elpm r24, Z elpm r24, Z+ [R] ld r24, Y+ ld r24, -Y [R] ld r24, X ld r24, X+ ld r24, -X pop r24
919x lds r25, 0x9190 ld r25, Z+ ld r25, -Z [R] lpm r25, Z lpm r25, Z+ elpm r25, Z elpm r25, Z+ [R] ld r25, Y+ ld r25, -Y [R] ld r25, X ld r25, X+ ld r25, -X pop r25
91Ax lds r26, 0x91A0 ld r26, Z+ ld r26, -Z [R] lpm r26, Z lpm r26, Z+ elpm r26, Z elpm r26, Z+ [R] ld r26, Y+ ld r26, -Y [R] ld r26, X ld r26, X+ ; undefined ld r26, -X ; undefined pop r26
91Bx lds r27, 0x91B0 ld r27, Z+ ld r27, -Z [R] lpm r27, Z lpm r27, Z+ elpm r27, Z elpm r27, Z+ [R] ld r27, Y+ ld r27, -Y [R] ld r27, X ld r27, X+ ; undefined ld r27, -X ; undefined pop r27
91Cx lds r28, 0x91C0 ld r28, Z+ ld r28, -Z [R] lpm r28, Z lpm r28, Z+ elpm r28, Z elpm r28, Z+ [R] ld r28, Y+ ; undefined ld r28, -Y ; undefined [R] ld r28, X ld r28, X+ ld r28, -X pop r28
91Dx lds r29, 0x91D0 ld r29, Z+ ld r29, -Z [R] lpm r29, Z lpm r29, Z+ elpm r29, Z elpm r29, Z+ [R] ld r29, Y+ ; undefined ld r29, -Y ; undefined [R] ld r29, X ld r29, X+ ld r29, -X pop r29
91Ex lds r30, 0x91E0 ld r30, Z+ ; undefined ld r30, -Z ; undefined [R] lpm r30, Z lpm r30, Z+ ; undefined elpm r30, Z elpm r30, Z+ ; undefined [R] ld r30, Y+ ld r30, -Y [R] ld r30, X ld r30, X+ ld r30, -X pop r30
91Fx lds r31, 0x91F0 ld r31, Z+ ; undefined ld r31, -Z ; undefined [R] lpm r31, Z lpm r31, Z+ ; undefined elpm r31, Z elpm r31, Z+ ; undefined [R] ld r31, Y+ ld r31, -Y [R] ld r31, X ld r31, X+ ld r31, -X pop r31

Red = instruction has undefined behavior (16)
Yellow = two-word instruction (16)
[R] = Reserved (48)

elpm - Extended Load from Program Memory (from RAMPZ + Z)
ld - LoaD register indirect from data space
lds - Load register direct from Data Space
lpm - Load register from Program Memory (from Z)
pop - POP one byte from stack into the register
^ summary

Opcodes 92xx (0x9200 - 0x92FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
920x sts 0x9200, r0 st Z+, r0 st -Z, r0 [R] st Y+, r0 st -Y, r0 [R] st X, r0 st X+, r0 st -X, r0 push r0
921x sts 0x9210, r1 st Z+, r1 st -Z, r1 [R] st Y+, r1 st -Y, r1 [R] st X, r1 st X+, r1 st -X, r1 push r1
922x sts 0x9220, r2 st Z+, r2 st -Z, r2 [R] st Y+, r2 st -Y, r2 [R] st X, r2 st X+, r2 st -X, r2 push r2
923x sts 0x9230, r3 st Z+, r3 st -Z, r3 [R] st Y+, r3 st -Y, r3 [R] st X, r3 st X+, r3 st -X, r3 push r3
924x sts 0x9240, r4 st Z+, r4 st -Z, r4 [R] st Y+, r4 st -Y, r4 [R] st X, r4 st X+, r4 st -X, r4 push r4
925x sts 0x9250, r5 st Z+, r5 st -Z, r5 [R] st Y+, r5 st -Y, r5 [R] st X, r5 st X+, r5 st -X, r5 push r5
926x sts 0x9260, r6 st Z+, r6 st -Z, r6 [R] st Y+, r6 st -Y, r6 [R] st X, r6 st X+, r6 st -X, r6 push r6
927x sts 0x9270, r7 st Z+, r7 st -Z, r7 [R] st Y+, r7 st -Y, r7 [R] st X, r7 st X+, r7 st -X, r7 push r7
928x sts 0x9280, r8 st Z+, r8 st -Z, r8 [R] st Y+, r8 st -Y, r8 [R] st X, r8 st X+, r8 st -X, r8 push r8
929x sts 0x9290, r9 st Z+, r9 st -Z, r9 [R] st Y+, r9 st -Y, r9 [R] st X, r9 st X+, r9 st -X, r9 push r9
92Ax sts 0x92A0, r10 st Z+, r10 st -Z, r10 [R] st Y+, r10 st -Y, r10 [R] st X, r10 st X+, r10 st -X, r10 push r10
92Bx sts 0x92B0, r11 st Z+, r11 st -Z, r11 [R] st Y+, r11 st -Y, r11 [R] st X, r11 st X+, r11 st -X, r11 push r11
92Cx sts 0x92C0, r12 st Z+, r12 st -Z, r12 [R] st Y+, r12 st -Y, r12 [R] st X, r12 st X+, r12 st -X, r12 push r12
92Dx sts 0x92D0, r13 st Z+, r13 st -Z, r13 [R] st Y+, r13 st -Y, r13 [R] st X, r13 st X+, r13 st -X, r13 push r13
92Ex sts 0x92E0, r14 st Z+, r14 st -Z, r14 [R] st Y+, r14 st -Y, r14 [R] st X, r14 st X+, r14 st -X, r14 push r14
92Fx sts 0x92F0, r15 st Z+, r15 st -Z, r15 [R] st Y+, r15 st -Y, r15 [R] st X, r15 st X+, r15 st -X, r15 push r15

Yellow = two-word instruction (16)
[R] = Reserved (112)

push - PUSH one register onto the stack
st - STore
sts - STore direct to data Space
^ summary

Opcodes 93xx (0x9300 - 0x93FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
930x sts 0x9300, r16 st Z+, r16 st -Z, r16 [R] st Y+, r16 st -Y, r16 [R] st X, r16 st X+, r16 st -X, r16 push r16
931x sts 0x9310, r17 st Z+, r17 st -Z, r17 [R] st Y+, r17 st -Y, r17 [R] st X, r17 st X+, r17 st -X, r17 push r17
932x sts 0x9320, r18 st Z+, r18 st -Z, r18 [R] st Y+, r18 st -Y, r18 [R] st X, r18 st X+, r18 st -X, r18 push r18
933x sts 0x9330, r19 st Z+, r19 st -Z, r19 [R] st Y+, r19 st -Y, r19 [R] st X, r19 st X+, r19 st -X, r19 push r19
934x sts 0x9340, r20 st Z+, r20 st -Z, r20 [R] st Y+, r20 st -Y, r20 [R] st X, r20 st X+, r20 st -X, r20 push r20
935x sts 0x9350, r21 st Z+, r21 st -Z, r21 [R] st Y+, r21 st -Y, r21 [R] st X, r21 st X+, r21 st -X, r21 push r21
936x sts 0x9360, r22 st Z+, r22 st -Z, r22 [R] st Y+, r22 st -Y, r22 [R] st X, r22 st X+, r22 st -X, r22 push r22
937x sts 0x9370, r23 st Z+, r23 st -Z, r23 [R] st Y+, r23 st -Y, r23 [R] st X, r23 st X+, r23 st -X, r23 push r23
938x sts 0x9380, r24 st Z+, r24 st -Z, r24 [R] st Y+, r24 st -Y, r24 [R] st X, r24 st X+, r24 st -X, r24 push r24
939x sts 0x9390, r25 st Z+, r25 st -Z, r25 [R] st Y+, r25 st -Y, r25 [R] st X, r25 st X+, r25 st -X, r25 push r25
93Ax sts 0x93A0, r26 st Z+, r26 st -Z, r26 [R] st Y+, r26 st -Y, r26 [R] st X, r26 st X+, r26 ; undefined st -X, r26 ; undefined push r26
93Bx sts 0x93B0, r27 st Z+, r27 st -Z, r27 [R] st Y+, r27 st -Y, r27 [R] st X, r27 st X+, r27 ; undefined st -X, r27 ; undefined push r27
93Cx sts 0x93C0, r28 st Z+, r28 st -Z, r28 [R] st Y+, r28 ; undefined st -Y, r28 ; undefined [R] st X, r28 st X+, r28 st -X, r28 push r28
93Dx sts 0x93D0, r29 st Z+, r29 st -Z, r29 [R] st Y+, r29 ; undefined st -Y, r29 ; undefined [R] st X, r29 st X+, r29 st -X, r29 push r29
93Ex sts 0x93E0, r30 st Z+, r30 ; undefined st -Z, r30 ; undefined [R] st Y+, r30 st -Y, r30 [R] st X, r30 st X+, r30 st -X, r30 push r30
93Fx sts 0x93F0, r31 st Z+, r31 ; undefined st -Z, r31 ; undefined [R] st Y+, r31 st -Y, r31 [R] st X, r31 st X+, r31 st -X, r31 push r31

Red = instruction has undefined behavior (12)
Yellow = two-word instruction (16)
[R] = Reserved (112)

push - PUSH one register onto the stack
st - STore
sts - STore direct to data Space
^ summary

Opcodes 94xx (0x9400 - 0x94FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
940x com r0 neg r0 swap r0 inc r0 [R] asr r0 lsr r0 ror r0 sec ijmp dec r0 des 0 jmp 0x12818 jmp 0x3281a call 0x1281c call 0x3281e
941x com r1 neg r1 swap r1 inc r1 [R] asr r1 lsr r1 ror r1 sez eijmp dec r1 des 1 jmp 0x52838 jmp 0x7283a call 0x5283c call 0x7283e
942x com r2 neg r2 swap r2 inc r2 [R] asr r2 lsr r2 ror r2 sen [R] dec r2 des 2 jmp 0x92858 jmp 0xb285a call 0x9285c call 0xb285e
943x com r3 neg r3 swap r3 inc r3 [R] asr r3 lsr r3 ror r3 sev [R] dec r3 des 3 jmp 0xd2878 jmp 0xf287a call 0xd287c call 0xf287e
944x com r4 neg r4 swap r4 inc r4 [R] asr r4 lsr r4 ror r4 ses [R] dec r4 des 4 jmp 0x112898 jmp 0x13289a call 0x11289c call 0x13289e
945x com r5 neg r5 swap r5 inc r5 [R] asr r5 lsr r5 ror r5 seh [R] dec r5 des 5 jmp 0x1528b8 jmp 0x1728ba call 0x1528bc call 0x1728be
946x com r6 neg r6 swap r6 inc r6 [R] asr r6 lsr r6 ror r6 set [R] dec r6 des 6 jmp 0x1928d8 jmp 0x1b28da call 0x1928dc call 0x1b28de
947x com r7 neg r7 swap r7 inc r7 [R] asr r7 lsr r7 ror r7 sei [R] dec r7 des 7 jmp 0x1d28f8 jmp 0x1f28fa call 0x1d28fc call 0x1f28fe
948x com r8 neg r8 swap r8 inc r8 [R] asr r8 lsr r8 ror r8 clc [R] dec r8 des 8 jmp 0x212918 jmp 0x23291a call 0x21291c call 0x23291e
949x com r9 neg r9 swap r9 inc r9 [R] asr r9 lsr r9 ror r9 clz [R] dec r9 des 9 jmp 0x252938 jmp 0x27293a call 0x25293c call 0x27293e
94Ax com r10 neg r10 swap r10 inc r10 [R] asr r10 lsr r10 ror r10 cln [R] dec r10 des 10 jmp 0x292958 jmp 0x2b295a call 0x29295c call 0x2b295e
94Bx com r11 neg r11 swap r11 inc r11 [R] asr r11 lsr r11 ror r11 clv [R] dec r11 des 11 jmp 0x2d2978 jmp 0x2f297a call 0x2d297c call 0x2f297e
94Cx com r12 neg r12 swap r12 inc r12 [R] asr r12 lsr r12 ror r12 cls [R] dec r12 des 12 jmp 0x312998 jmp 0x33299a call 0x31299c call 0x33299e
94Dx com r13 neg r13 swap r13 inc r13 [R] asr r13 lsr r13 ror r13 clh [R] dec r13 des 13 jmp 0x3529b8 jmp 0x3729ba call 0x3529bc call 0x3729be
94Ex com r14 neg r14 swap r14 inc r14 [R] asr r14 lsr r14 ror r14 clt [R] dec r14 des 14 jmp 0x3929d8 jmp 0x3b29da call 0x3929dc call 0x3b29de
94Fx com r15 neg r15 swap r15 inc r15 [R] asr r15 lsr r15 ror r15 cli [R] dec r15 des 15 jmp 0x3d29f8 jmp 0x3f29fa call 0x3d29fc call 0x3f29fe

Green = opcode newly defined for ATxmega (16)
Yellow = two-word instruction (64)
[R] = Reserved (30)

asr - Arithmetic Shift Right register by one bit
call - CALL a subroutine at an absolute address
clc - CLear Carry flag in SREG
clh - CLear Half-carry flag in SREG
cli - CLear global Interrupt-enable flag in SREG
cln - CLear Negative flag in SREG
cls - CLear Signed flag in SREG
clt - CLear T flag in SREG
clv - CLear oVerfloag flag in SREG
clz - CLear Zero flag in SREG
com - COMplement - flip all the bits in the register
dec - DECrement the register by one
des - Data Encryption Standard - perform one round of DES encryption or decryption
eijmp - Extended Indirect JuMP (to EIND + Z)
ijmp - Indirect JuMP (to Z)
inc - INCrement the register by one
jmp - JuMP to the absolute address
lsr - Logical Shift Right one bit
neg - NEGate the register
ror - ROtate register Right through carry
sec - SEt the Carry flag in SREG
seh - SEt the Half-carry flag in SREG
sei - SEt the Interrupt-enable flag in SREG
sen - SEt the Negative flag in SREG
ses - SEt the Signed flag in SREG
set - SEt the T flag in SREG
sev - SEt the oVerflow flag in SREG
sez - SEt the Zero flag in SREG
swap - SWAP the register's two nibbles
^ summary

Opcodes 95xx (0x9500 - 0x95FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
950x com r16 neg r16 swap r16 inc r16 [R] asr r16 lsr r16 ror r16 ret icall dec r16 [R] jmp 0x412a18 jmp 0x432a1a call 0x412a1c call 0x432a1e
951x com r17 neg r17 swap r17 inc r17 [R] asr r17 lsr r17 ror r17 reti eicall dec r17 [R] jmp 0x452a38 jmp 0x472a3a call 0x452a3c call 0x472a3e
952x com r18 neg r18 swap r18 inc r18 [R] asr r18 lsr r18 ror r18 [R] dec r18 [R] jmp 0x492a58 jmp 0x4b2a5a call 0x492a5c call 0x4b2a5e
953x com r19 neg r19 swap r19 inc r19 [R] asr r19 lsr r19 ror r19 [R] dec r19 [R] jmp 0x4d2a78 jmp 0x4f2a7a call 0x4d2a7c call 0x4f2a7e
954x com r20 neg r20 swap r20 inc r20 [R] asr r20 lsr r20 ror r20 [R] dec r20 [R] jmp 0x512a98 jmp 0x532a9a call 0x512a9c call 0x532a9e
955x com r21 neg r21 swap r21 inc r21 [R] asr r21 lsr r21 ror r21 [R] dec r21 [R] jmp 0x552ab8 jmp 0x572aba call 0x552abc call 0x572abe
956x com r22 neg r22 swap r22 inc r22 [R] asr r22 lsr r22 ror r22 [R] dec r22 [R] jmp 0x592ad8 jmp 0x5b2ada call 0x592adc call 0x5b2ade
957x com r23 neg r23 swap r23 inc r23 [R] asr r23 lsr r23 ror r23 [R] dec r23 [R] jmp 0x5d2af8 jmp 0x5f2afa call 0x5d2afc call 0x5f2afe
958x com r24 neg r24 swap r24 inc r24 [R] asr r24 lsr r24 ror r24 sleep [R] dec r24 [R] jmp 0x612b18 jmp 0x632b1a call 0x612b1c call 0x632b1e
959x com r25 neg r25 swap r25 inc r25 [R] asr r25 lsr r25 ror r25 break [R] dec r25 [R] jmp 0x652b38 jmp 0x672b3a call 0x652b3c call 0x672b3e
95Ax com r26 neg r26 swap r26 inc r26 [R] asr r26 lsr r26 ror r26 wdr [R] dec r26 [R] jmp 0x692b58 jmp 0x6b2b5a call 0x692b5c call 0x6b2b5e
95Bx com r27 neg r27 swap r27 inc r27 [R] asr r27 lsr r27 ror r27 [R] dec r27 [R] jmp 0x6d2b78 jmp 0x6f2b7a call 0x6d2b7c call 0x6f2b7e
95Cx com r28 neg r28 swap r28 inc r28 [R] asr r28 lsr r28 ror r28 lpm [R] dec r28 [R] jmp 0x712b98 jmp 0x732b9a call 0x712b9c call 0x732b9e
95Dx com r29 neg r29 swap r29 inc r29 [R] asr r29 lsr r29 ror r29 elpm [R] dec r29 [R] jmp 0x752bb8 jmp 0x772bba call 0x752bbc call 0x772bbe
95Ex com r30 neg r30 swap r30 inc r30 [R] asr r30 lsr r30 ror r30 spm [R] dec r30 [R] jmp 0x792bd8 jmp 0x7b2bda call 0x792bdc call 0x7b2bde
95Fx com r31 neg r31 swap r31 inc r31 [R] asr r31 lsr r31 ror r31 spm [R] dec r31 [R] jmp 0x7d2bf8 jmp 0x7f2bfa call 0x7d2bfc call 0x7f2bfe

Green = opcode newly defined for ATxmega (1)
Yellow = two-word instruction (64)
[R] = Reserved (53)

asr - Arithmetic Shift Right register by one bit
break - stop for debugger
call - CALL a subroutine at an absolute address
com - COMplement - flip all the bits in the register
dec - DECrement the register by one
eicall - Extended Indirect CALL to subroutine (at EIND + Z)
elpm - Extended Load from Program Memory (from RAMPZ + Z)
icall - Indirect CALL to subroutine (at Z)
inc - INCrement the register by one
jmp - JuMP to the absolute address
lpm - Load register from Program Memory (from Z)
lsr - Logical Shift Right one bit
neg - NEGate the register
ret - RETurn from subroutine
reti - RETurn from Interrupt (and re-enable interrupts)
ror - ROtate register Right through carry
sleep - sleep the processor to save power
spm - Store into Program Memory
swap - SWAP the register's two nibbles
wdr - WatchDog Reset
^ summary

Opcodes F0xx (0xF000 - 0xF0FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F00x brcs .+0 breq .+0 brmi .+0 brvs .+0 brlt .+0 brhs .+0 brts .+0 brie .+0 brcs .+2 breq .+2 brmi .+2 brvs .+2 brlt .+2 brhs .+2 brts .+2 brie .+2
F01x brcs .+4 breq .+4 brmi .+4 brvs .+4 brlt .+4 brhs .+4 brts .+4 brie .+4 brcs .+6 breq .+6 brmi .+6 brvs .+6 brlt .+6 brhs .+6 brts .+6 brie .+6
F02x brcs .+8 breq .+8 brmi .+8 brvs .+8 brlt .+8 brhs .+8 brts .+8 brie .+8 brcs .+10 breq .+10 brmi .+10 brvs .+10 brlt .+10 brhs .+10 brts .+10 brie .+10
F03x brcs .+12 breq .+12 brmi .+12 brvs .+12 brlt .+12 brhs .+12 brts .+12 brie .+12 brcs .+14 breq .+14 brmi .+14 brvs .+14 brlt .+14 brhs .+14 brts .+14 brie .+14
F04x brcs .+16 breq .+16 brmi .+16 brvs .+16 brlt .+16 brhs .+16 brts .+16 brie .+16 brcs .+18 breq .+18 brmi .+18 brvs .+18 brlt .+18 brhs .+18 brts .+18 brie .+18
F05x brcs .+20 breq .+20 brmi .+20 brvs .+20 brlt .+20 brhs .+20 brts .+20 brie .+20 brcs .+22 breq .+22 brmi .+22 brvs .+22 brlt .+22 brhs .+22 brts .+22 brie .+22
F06x brcs .+24 breq .+24 brmi .+24 brvs .+24 brlt .+24 brhs .+24 brts .+24 brie .+24 brcs .+26 breq .+26 brmi .+26 brvs .+26 brlt .+26 brhs .+26 brts .+26 brie .+26
F07x brcs .+28 breq .+28 brmi .+28 brvs .+28 brlt .+28 brhs .+28 brts .+28 brie .+28 brcs .+30 breq .+30 brmi .+30 brvs .+30 brlt .+30 brhs .+30 brts .+30 brie .+30
F08x brcs .+32 breq .+32 brmi .+32 brvs .+32 brlt .+32 brhs .+32 brts .+32 brie .+32 brcs .+34 breq .+34 brmi .+34 brvs .+34 brlt .+34 brhs .+34 brts .+34 brie .+34
F09x brcs .+36 breq .+36 brmi .+36 brvs .+36 brlt .+36 brhs .+36 brts .+36 brie .+36 brcs .+38 breq .+38 brmi .+38 brvs .+38 brlt .+38 brhs .+38 brts .+38 brie .+38
F0Ax brcs .+40 breq .+40 brmi .+40 brvs .+40 brlt .+40 brhs .+40 brts .+40 brie .+40 brcs .+42 breq .+42 brmi .+42 brvs .+42 brlt .+42 brhs .+42 brts .+42 brie .+42
F0Bx brcs .+44 breq .+44 brmi .+44 brvs .+44 brlt .+44 brhs .+44 brts .+44 brie .+44 brcs .+46 breq .+46 brmi .+46 brvs .+46 brlt .+46 brhs .+46 brts .+46 brie .+46
F0Cx brcs .+48 breq .+48 brmi .+48 brvs .+48 brlt .+48 brhs .+48 brts .+48 brie .+48 brcs .+50 breq .+50 brmi .+50 brvs .+50 brlt .+50 brhs .+50 brts .+50 brie .+50
F0Dx brcs .+52 breq .+52 brmi .+52 brvs .+52 brlt .+52 brhs .+52 brts .+52 brie .+52 brcs .+54 breq .+54 brmi .+54 brvs .+54 brlt .+54 brhs .+54 brts .+54 brie .+54
F0Ex brcs .+56 breq .+56 brmi .+56 brvs .+56 brlt .+56 brhs .+56 brts .+56 brie .+56 brcs .+58 breq .+58 brmi .+58 brvs .+58 brlt .+58 brhs .+58 brts .+58 brie .+58
F0Fx brcs .+60 breq .+60 brmi .+60 brvs .+60 brlt .+60 brhs .+60 brts .+60 brie .+60 brcs .+62 breq .+62 brmi .+62 brvs .+62 brlt .+62 brhs .+62 brts .+62 brie .+62
brcs - BRanch if Carry Set
breq - BRanch if EQual (Z flag set)
brhs - BRanch if Half-carry Set
brie - BRanch if global Interrupt flag enabled
brlt - BRanch if Less Than (signed)
brmi - BRanch if MInus (N flag set)
brts - BRanch if T flag Set in SREG
brvs - BRanch if oVerflow flag Set in SREG
^ summary

Opcodes F1xx (0xF100 - 0xF1FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F10x brcs .+64 breq .+64 brmi .+64 brvs .+64 brlt .+64 brhs .+64 brts .+64 brie .+64 brcs .+66 breq .+66 brmi .+66 brvs .+66 brlt .+66 brhs .+66 brts .+66 brie .+66
F11x brcs .+68 breq .+68 brmi .+68 brvs .+68 brlt .+68 brhs .+68 brts .+68 brie .+68 brcs .+70 breq .+70 brmi .+70 brvs .+70 brlt .+70 brhs .+70 brts .+70 brie .+70
F12x brcs .+72 breq .+72 brmi .+72 brvs .+72 brlt .+72 brhs .+72 brts .+72 brie .+72 brcs .+74 breq .+74 brmi .+74 brvs .+74 brlt .+74 brhs .+74 brts .+74 brie .+74
F13x brcs .+76 breq .+76 brmi .+76 brvs .+76 brlt .+76 brhs .+76 brts .+76 brie .+76 brcs .+78 breq .+78 brmi .+78 brvs .+78 brlt .+78 brhs .+78 brts .+78 brie .+78
F14x brcs .+80 breq .+80 brmi .+80 brvs .+80 brlt .+80 brhs .+80 brts .+80 brie .+80 brcs .+82 breq .+82 brmi .+82 brvs .+82 brlt .+82 brhs .+82 brts .+82 brie .+82
F15x brcs .+84 breq .+84 brmi .+84 brvs .+84 brlt .+84 brhs .+84 brts .+84 brie .+84 brcs .+86 breq .+86 brmi .+86 brvs .+86 brlt .+86 brhs .+86 brts .+86 brie .+86
F16x brcs .+88 breq .+88 brmi .+88 brvs .+88 brlt .+88 brhs .+88 brts .+88 brie .+88 brcs .+90 breq .+90 brmi .+90 brvs .+90 brlt .+90 brhs .+90 brts .+90 brie .+90
F17x brcs .+92 breq .+92 brmi .+92 brvs .+92 brlt .+92 brhs .+92 brts .+92 brie .+92 brcs .+94 breq .+94 brmi .+94 brvs .+94 brlt .+94 brhs .+94 brts .+94 brie .+94
F18x brcs .+96 breq .+96 brmi .+96 brvs .+96 brlt .+96 brhs .+96 brts .+96 brie .+96 brcs .+98 breq .+98 brmi .+98 brvs .+98 brlt .+98 brhs .+98 brts .+98 brie .+98
F19x brcs .+100 breq .+100 brmi .+100 brvs .+100 brlt .+100 brhs .+100 brts .+100 brie .+100 brcs .+102 breq .+102 brmi .+102 brvs .+102 brlt .+102 brhs .+102 brts .+102 brie .+102
F1Ax brcs .+104 breq .+104 brmi .+104 brvs .+104 brlt .+104 brhs .+104 brts .+104 brie .+104 brcs .+106 breq .+106 brmi .+106 brvs .+106 brlt .+106 brhs .+106 brts .+106 brie .+106
F1Bx brcs .+108 breq .+108 brmi .+108 brvs .+108 brlt .+108 brhs .+108 brts .+108 brie .+108 brcs .+110 breq .+110 brmi .+110 brvs .+110 brlt .+110 brhs .+110 brts .+110 brie .+110
F1Cx brcs .+112 breq .+112 brmi .+112 brvs .+112 brlt .+112 brhs .+112 brts .+112 brie .+112 brcs .+114 breq .+114 brmi .+114 brvs .+114 brlt .+114 brhs .+114 brts .+114 brie .+114
F1Dx brcs .+116 breq .+116 brmi .+116 brvs .+116 brlt .+116 brhs .+116 brts .+116 brie .+116 brcs .+118 breq .+118 brmi .+118 brvs .+118 brlt .+118 brhs .+118 brts .+118 brie .+118
F1Ex brcs .+120 breq .+120 brmi .+120 brvs .+120 brlt .+120 brhs .+120 brts .+120 brie .+120 brcs .+122 breq .+122 brmi .+122 brvs .+122 brlt .+122 brhs .+122 brts .+122 brie .+122
F1Fx brcs .+124 breq .+124 brmi .+124 brvs .+124 brlt .+124 brhs .+124 brts .+124 brie .+124 brcs .+126 breq .+126 brmi .+126 brvs .+126 brlt .+126 brhs .+126 brts .+126 brie .+126
brcs - BRanch if Carry Set
breq - BRanch if EQual (Z flag set)
brhs - BRanch if Half-carry Set
brie - BRanch if global Interrupt flag enabled
brlt - BRanch if Less Than (signed)
brmi - BRanch if MInus (N flag set)
brts - BRanch if T flag Set in SREG
brvs - BRanch if oVerflow flag Set in SREG
^ summary

Opcodes F2xx (0xF200 - 0xF2FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F20x brcs .-128 breq .-128 brmi .-128 brvs .-128 brlt .-128 brhs .-128 brts .-128 brie .-128 brcs .-126 breq .-126 brmi .-126 brvs .-126 brlt .-126 brhs .-126 brts .-126 brie .-126
F21x brcs .-124 breq .-124 brmi .-124 brvs .-124 brlt .-124 brhs .-124 brts .-124 brie .-124 brcs .-122 breq .-122 brmi .-122 brvs .-122 brlt .-122 brhs .-122 brts .-122 brie .-122
F22x brcs .-120 breq .-120 brmi .-120 brvs .-120 brlt .-120 brhs .-120 brts .-120 brie .-120 brcs .-118 breq .-118 brmi .-118 brvs .-118 brlt .-118 brhs .-118 brts .-118 brie .-118
F23x brcs .-116 breq .-116 brmi .-116 brvs .-116 brlt .-116 brhs .-116 brts .-116 brie .-116 brcs .-114 breq .-114 brmi .-114 brvs .-114 brlt .-114 brhs .-114 brts .-114 brie .-114
F24x brcs .-112 breq .-112 brmi .-112 brvs .-112 brlt .-112 brhs .-112 brts .-112 brie .-112 brcs .-110 breq .-110 brmi .-110 brvs .-110 brlt .-110 brhs .-110 brts .-110 brie .-110
F25x brcs .-108 breq .-108 brmi .-108 brvs .-108 brlt .-108 brhs .-108 brts .-108 brie .-108 brcs .-106 breq .-106 brmi .-106 brvs .-106 brlt .-106 brhs .-106 brts .-106 brie .-106
F26x brcs .-104 breq .-104 brmi .-104 brvs .-104 brlt .-104 brhs .-104 brts .-104 brie .-104 brcs .-102 breq .-102 brmi .-102 brvs .-102 brlt .-102 brhs .-102 brts .-102 brie .-102
F27x brcs .-100 breq .-100 brmi .-100 brvs .-100 brlt .-100 brhs .-100 brts .-100 brie .-100 brcs .-98 breq .-98 brmi .-98 brvs .-98 brlt .-98 brhs .-98 brts .-98 brie .-98
F28x brcs .-96 breq .-96 brmi .-96 brvs .-96 brlt .-96 brhs .-96 brts .-96 brie .-96 brcs .-94 breq .-94 brmi .-94 brvs .-94 brlt .-94 brhs .-94 brts .-94 brie .-94
F29x brcs .-92 breq .-92 brmi .-92 brvs .-92 brlt .-92 brhs .-92 brts .-92 brie .-92 brcs .-90 breq .-90 brmi .-90 brvs .-90 brlt .-90 brhs .-90 brts .-90 brie .-90
F2Ax brcs .-88 breq .-88 brmi .-88 brvs .-88 brlt .-88 brhs .-88 brts .-88 brie .-88 brcs .-86 breq .-86 brmi .-86 brvs .-86 brlt .-86 brhs .-86 brts .-86 brie .-86
F2Bx brcs .-84 breq .-84 brmi .-84 brvs .-84 brlt .-84 brhs .-84 brts .-84 brie .-84 brcs .-82 breq .-82 brmi .-82 brvs .-82 brlt .-82 brhs .-82 brts .-82 brie .-82
F2Cx brcs .-80 breq .-80 brmi .-80 brvs .-80 brlt .-80 brhs .-80 brts .-80 brie .-80 brcs .-78 breq .-78 brmi .-78 brvs .-78 brlt .-78 brhs .-78 brts .-78 brie .-78
F2Dx brcs .-76 breq .-76 brmi .-76 brvs .-76 brlt .-76 brhs .-76 brts .-76 brie .-76 brcs .-74 breq .-74 brmi .-74 brvs .-74 brlt .-74 brhs .-74 brts .-74 brie .-74
F2Ex brcs .-72 breq .-72 brmi .-72 brvs .-72 brlt .-72 brhs .-72 brts .-72 brie .-72 brcs .-70 breq .-70 brmi .-70 brvs .-70 brlt .-70 brhs .-70 brts .-70 brie .-70
F2Fx brcs .-68 breq .-68 brmi .-68 brvs .-68 brlt .-68 brhs .-68 brts .-68 brie .-68 brcs .-66 breq .-66 brmi .-66 brvs .-66 brlt .-66 brhs .-66 brts .-66 brie .-66
brcs - BRanch if Carry Set
breq - BRanch if EQual (Z flag set)
brhs - BRanch if Half-carry Set
brie - BRanch if global Interrupt flag enabled
brlt - BRanch if Less Than (signed)
brmi - BRanch if MInus (N flag set)
brts - BRanch if T flag Set in SREG
brvs - BRanch if oVerflow flag Set in SREG
^ summary

Opcodes F3xx (0xF300 - 0xF3FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F30x brcs .-64 breq .-64 brmi .-64 brvs .-64 brlt .-64 brhs .-64 brts .-64 brie .-64 brcs .-62 breq .-62 brmi .-62 brvs .-62 brlt .-62 brhs .-62 brts .-62 brie .-62
F31x brcs .-60 breq .-60 brmi .-60 brvs .-60 brlt .-60 brhs .-60 brts .-60 brie .-60 brcs .-58 breq .-58 brmi .-58 brvs .-58 brlt .-58 brhs .-58 brts .-58 brie .-58
F32x brcs .-56 breq .-56 brmi .-56 brvs .-56 brlt .-56 brhs .-56 brts .-56 brie .-56 brcs .-54 breq .-54 brmi .-54 brvs .-54 brlt .-54 brhs .-54 brts .-54 brie .-54
F33x brcs .-52 breq .-52 brmi .-52 brvs .-52 brlt .-52 brhs .-52 brts .-52 brie .-52 brcs .-50 breq .-50 brmi .-50 brvs .-50 brlt .-50 brhs .-50 brts .-50 brie .-50
F34x brcs .-48 breq .-48 brmi .-48 brvs .-48 brlt .-48 brhs .-48 brts .-48 brie .-48 brcs .-46 breq .-46 brmi .-46 brvs .-46 brlt .-46 brhs .-46 brts .-46 brie .-46
F35x brcs .-44 breq .-44 brmi .-44 brvs .-44 brlt .-44 brhs .-44 brts .-44 brie .-44 brcs .-42 breq .-42 brmi .-42 brvs .-42 brlt .-42 brhs .-42 brts .-42 brie .-42
F36x brcs .-40 breq .-40 brmi .-40 brvs .-40 brlt .-40 brhs .-40 brts .-40 brie .-40 brcs .-38 breq .-38 brmi .-38 brvs .-38 brlt .-38 brhs .-38 brts .-38 brie .-38
F37x brcs .-36 breq .-36 brmi .-36 brvs .-36 brlt .-36 brhs .-36 brts .-36 brie .-36 brcs .-34 breq .-34 brmi .-34 brvs .-34 brlt .-34 brhs .-34 brts .-34 brie .-34
F38x brcs .-32 breq .-32 brmi .-32 brvs .-32 brlt .-32 brhs .-32 brts .-32 brie .-32 brcs .-30 breq .-30 brmi .-30 brvs .-30 brlt .-30 brhs .-30 brts .-30 brie .-30
F39x brcs .-28 breq .-28 brmi .-28 brvs .-28 brlt .-28 brhs .-28 brts .-28 brie .-28 brcs .-26 breq .-26 brmi .-26 brvs .-26 brlt .-26 brhs .-26 brts .-26 brie .-26
F3Ax brcs .-24 breq .-24 brmi .-24 brvs .-24 brlt .-24 brhs .-24 brts .-24 brie .-24 brcs .-22 breq .-22 brmi .-22 brvs .-22 brlt .-22 brhs .-22 brts .-22 brie .-22
F3Bx brcs .-20 breq .-20 brmi .-20 brvs .-20 brlt .-20 brhs .-20 brts .-20 brie .-20 brcs .-18 breq .-18 brmi .-18 brvs .-18 brlt .-18 brhs .-18 brts .-18 brie .-18
F3Cx brcs .-16 breq .-16 brmi .-16 brvs .-16 brlt .-16 brhs .-16 brts .-16 brie .-16 brcs .-14 breq .-14 brmi .-14 brvs .-14 brlt .-14 brhs .-14 brts .-14 brie .-14
F3Dx brcs .-12 breq .-12 brmi .-12 brvs .-12 brlt .-12 brhs .-12 brts .-12 brie .-12 brcs .-10 breq .-10 brmi .-10 brvs .-10 brlt .-10 brhs .-10 brts .-10 brie .-10
F3Ex brcs .-8 breq .-8 brmi .-8 brvs .-8 brlt .-8 brhs .-8 brts .-8 brie .-8 brcs .-6 breq .-6 brmi .-6 brvs .-6 brlt .-6 brhs .-6 brts .-6 brie .-6
F3Fx brcs .-4 breq .-4 brmi .-4 brvs .-4 brlt .-4 brhs .-4 brts .-4 brie .-4 brcs .-2 breq .-2 brmi .-2 brvs .-2 brlt .-2 brhs .-2 brts .-2 brie .-2
brcs - BRanch if Carry Set
breq - BRanch if EQual (Z flag set)
brhs - BRanch if Half-carry Set
brie - BRanch if global Interrupt flag enabled
brlt - BRanch if Less Than (signed)
brmi - BRanch if MInus (N flag set)
brts - BRanch if T flag Set in SREG
brvs - BRanch if oVerflow flag Set in SREG
^ summary

Opcodes F4xx (0xF400 - 0xF4FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F40x brcc .+0 brne .+0 brpl .+0 brvc .+0 brge .+0 brhc .+0 brtc .+0 brid .+0 brcc .+2 brne .+2 brpl .+2 brvc .+2 brge .+2 brhc .+2 brtc .+2 brid .+2
F41x brcc .+4 brne .+4 brpl .+4 brvc .+4 brge .+4 brhc .+4 brtc .+4 brid .+4 brcc .+6 brne .+6 brpl .+6 brvc .+6 brge .+6 brhc .+6 brtc .+6 brid .+6
F42x brcc .+8 brne .+8 brpl .+8 brvc .+8 brge .+8 brhc .+8 brtc .+8 brid .+8 brcc .+10 brne .+10 brpl .+10 brvc .+10 brge .+10 brhc .+10 brtc .+10 brid .+10
F43x brcc .+12 brne .+12 brpl .+12 brvc .+12 brge .+12 brhc .+12 brtc .+12 brid .+12 brcc .+14 brne .+14 brpl .+14 brvc .+14 brge .+14 brhc .+14 brtc .+14 brid .+14
F44x brcc .+16 brne .+16 brpl .+16 brvc .+16 brge .+16 brhc .+16 brtc .+16 brid .+16 brcc .+18 brne .+18 brpl .+18 brvc .+18 brge .+18 brhc .+18 brtc .+18 brid .+18
F45x brcc .+20 brne .+20 brpl .+20 brvc .+20 brge .+20 brhc .+20 brtc .+20 brid .+20 brcc .+22 brne .+22 brpl .+22 brvc .+22 brge .+22 brhc .+22 brtc .+22 brid .+22
F46x brcc .+24 brne .+24 brpl .+24 brvc .+24 brge .+24 brhc .+24 brtc .+24 brid .+24 brcc .+26 brne .+26 brpl .+26 brvc .+26 brge .+26 brhc .+26 brtc .+26 brid .+26
F47x brcc .+28 brne .+28 brpl .+28 brvc .+28 brge .+28 brhc .+28 brtc .+28 brid .+28 brcc .+30 brne .+30 brpl .+30 brvc .+30 brge .+30 brhc .+30 brtc .+30 brid .+30
F48x brcc .+32 brne .+32 brpl .+32 brvc .+32 brge .+32 brhc .+32 brtc .+32 brid .+32 brcc .+34 brne .+34 brpl .+34 brvc .+34 brge .+34 brhc .+34 brtc .+34 brid .+34
F49x brcc .+36 brne .+36 brpl .+36 brvc .+36 brge .+36 brhc .+36 brtc .+36 brid .+36 brcc .+38 brne .+38 brpl .+38 brvc .+38 brge .+38 brhc .+38 brtc .+38 brid .+38
F4Ax brcc .+40 brne .+40 brpl .+40 brvc .+40 brge .+40 brhc .+40 brtc .+40 brid .+40 brcc .+42 brne .+42 brpl .+42 brvc .+42 brge .+42 brhc .+42 brtc .+42 brid .+42
F4Bx brcc .+44 brne .+44 brpl .+44 brvc .+44 brge .+44 brhc .+44 brtc .+44 brid .+44 brcc .+46 brne .+46 brpl .+46 brvc .+46 brge .+46 brhc .+46 brtc .+46 brid .+46
F4Cx brcc .+48 brne .+48 brpl .+48 brvc .+48 brge .+48 brhc .+48 brtc .+48 brid .+48 brcc .+50 brne .+50 brpl .+50 brvc .+50 brge .+50 brhc .+50 brtc .+50 brid .+50
F4Dx brcc .+52 brne .+52 brpl .+52 brvc .+52 brge .+52 brhc .+52 brtc .+52 brid .+52 brcc .+54 brne .+54 brpl .+54 brvc .+54 brge .+54 brhc .+54 brtc .+54 brid .+54
F4Ex brcc .+56 brne .+56 brpl .+56 brvc .+56 brge .+56 brhc .+56 brtc .+56 brid .+56 brcc .+58 brne .+58 brpl .+58 brvc .+58 brge .+58 brhc .+58 brtc .+58 brid .+58
F4Fx brcc .+60 brne .+60 brpl .+60 brvc .+60 brge .+60 brhc .+60 brtc .+60 brid .+60 brcc .+62 brne .+62 brpl .+62 brvc .+62 brge .+62 brhc .+62 brtc .+62 brid .+62
brcc - BRanch if Carry Clear
brge - BRanch if Greater or Equal (signed)
brhc - BRanch if Half-carry Clear
brid - BRanch if global Interrupt flag disabled
brne - BRanch if Not Equal (Z flag clear)
brpl - BRanch if PLus (N flag clear)
brtc - BRanch if T flag Clear in SREG
brvc - BRanch if oVerflow flag Clear in SREG
^ summary

Opcodes F5xx (0xF500 - 0xF5FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F50x brcc .+64 brne .+64 brpl .+64 brvc .+64 brge .+64 brhc .+64 brtc .+64 brid .+64 brcc .+66 brne .+66 brpl .+66 brvc .+66 brge .+66 brhc .+66 brtc .+66 brid .+66
F51x brcc .+68 brne .+68 brpl .+68 brvc .+68 brge .+68 brhc .+68 brtc .+68 brid .+68 brcc .+70 brne .+70 brpl .+70 brvc .+70 brge .+70 brhc .+70 brtc .+70 brid .+70
F52x brcc .+72 brne .+72 brpl .+72 brvc .+72 brge .+72 brhc .+72 brtc .+72 brid .+72 brcc .+74 brne .+74 brpl .+74 brvc .+74 brge .+74 brhc .+74 brtc .+74 brid .+74
F53x brcc .+76 brne .+76 brpl .+76 brvc .+76 brge .+76 brhc .+76 brtc .+76 brid .+76 brcc .+78 brne .+78 brpl .+78 brvc .+78 brge .+78 brhc .+78 brtc .+78 brid .+78
F54x brcc .+80 brne .+80 brpl .+80 brvc .+80 brge .+80 brhc .+80 brtc .+80 brid .+80 brcc .+82 brne .+82 brpl .+82 brvc .+82 brge .+82 brhc .+82 brtc .+82 brid .+82
F55x brcc .+84 brne .+84 brpl .+84 brvc .+84 brge .+84 brhc .+84 brtc .+84 brid .+84 brcc .+86 brne .+86 brpl .+86 brvc .+86 brge .+86 brhc .+86 brtc .+86 brid .+86
F56x brcc .+88 brne .+88 brpl .+88 brvc .+88 brge .+88 brhc .+88 brtc .+88 brid .+88 brcc .+90 brne .+90 brpl .+90 brvc .+90 brge .+90 brhc .+90 brtc .+90 brid .+90
F57x brcc .+92 brne .+92 brpl .+92 brvc .+92 brge .+92 brhc .+92 brtc .+92 brid .+92 brcc .+94 brne .+94 brpl .+94 brvc .+94 brge .+94 brhc .+94 brtc .+94 brid .+94
F58x brcc .+96 brne .+96 brpl .+96 brvc .+96 brge .+96 brhc .+96 brtc .+96 brid .+96 brcc .+98 brne .+98 brpl .+98 brvc .+98 brge .+98 brhc .+98 brtc .+98 brid .+98
F59x brcc .+100 brne .+100 brpl .+100 brvc .+100 brge .+100 brhc .+100 brtc .+100 brid .+100 brcc .+102 brne .+102 brpl .+102 brvc .+102 brge .+102 brhc .+102 brtc .+102 brid .+102
F5Ax brcc .+104 brne .+104 brpl .+104 brvc .+104 brge .+104 brhc .+104 brtc .+104 brid .+104 brcc .+106 brne .+106 brpl .+106 brvc .+106 brge .+106 brhc .+106 brtc .+106 brid .+106
F5Bx brcc .+108 brne .+108 brpl .+108 brvc .+108 brge .+108 brhc .+108 brtc .+108 brid .+108 brcc .+110 brne .+110 brpl .+110 brvc .+110 brge .+110 brhc .+110 brtc .+110 brid .+110
F5Cx brcc .+112 brne .+112 brpl .+112 brvc .+112 brge .+112 brhc .+112 brtc .+112 brid .+112 brcc .+114 brne .+114 brpl .+114 brvc .+114 brge .+114 brhc .+114 brtc .+114 brid .+114
F5Dx brcc .+116 brne .+116 brpl .+116 brvc .+116 brge .+116 brhc .+116 brtc .+116 brid .+116 brcc .+118 brne .+118 brpl .+118 brvc .+118 brge .+118 brhc .+118 brtc .+118 brid .+118
F5Ex brcc .+120 brne .+120 brpl .+120 brvc .+120 brge .+120 brhc .+120 brtc .+120 brid .+120 brcc .+122 brne .+122 brpl .+122 brvc .+122 brge .+122 brhc .+122 brtc .+122 brid .+122
F5Fx brcc .+124 brne .+124 brpl .+124 brvc .+124 brge .+124 brhc .+124 brtc .+124 brid .+124 brcc .+126 brne .+126 brpl .+126 brvc .+126 brge .+126 brhc .+126 brtc .+126 brid .+126
brcc - BRanch if Carry Clear
brge - BRanch if Greater or Equal (signed)
brhc - BRanch if Half-carry Clear
brid - BRanch if global Interrupt flag disabled
brne - BRanch if Not Equal (Z flag clear)
brpl - BRanch if PLus (N flag clear)
brtc - BRanch if T flag Clear in SREG
brvc - BRanch if oVerflow flag Clear in SREG
^ summary

Opcodes F6xx (0xF600 - 0xF6FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F60x brcc .-128 brne .-128 brpl .-128 brvc .-128 brge .-128 brhc .-128 brtc .-128 brid .-128 brcc .-126 brne .-126 brpl .-126 brvc .-126 brge .-126 brhc .-126 brtc .-126 brid .-126
F61x brcc .-124 brne .-124 brpl .-124 brvc .-124 brge .-124 brhc .-124 brtc .-124 brid .-124 brcc .-122 brne .-122 brpl .-122 brvc .-122 brge .-122 brhc .-122 brtc .-122 brid .-122
F62x brcc .-120 brne .-120 brpl .-120 brvc .-120 brge .-120 brhc .-120 brtc .-120 brid .-120 brcc .-118 brne .-118 brpl .-118 brvc .-118 brge .-118 brhc .-118 brtc .-118 brid .-118
F63x brcc .-116 brne .-116 brpl .-116 brvc .-116 brge .-116 brhc .-116 brtc .-116 brid .-116 brcc .-114 brne .-114 brpl .-114 brvc .-114 brge .-114 brhc .-114 brtc .-114 brid .-114
F64x brcc .-112 brne .-112 brpl .-112 brvc .-112 brge .-112 brhc .-112 brtc .-112 brid .-112 brcc .-110 brne .-110 brpl .-110 brvc .-110 brge .-110 brhc .-110 brtc .-110 brid .-110
F65x brcc .-108 brne .-108 brpl .-108 brvc .-108 brge .-108 brhc .-108 brtc .-108 brid .-108 brcc .-106 brne .-106 brpl .-106 brvc .-106 brge .-106 brhc .-106 brtc .-106 brid .-106
F66x brcc .-104 brne .-104 brpl .-104 brvc .-104 brge .-104 brhc .-104 brtc .-104 brid .-104 brcc .-102 brne .-102 brpl .-102 brvc .-102 brge .-102 brhc .-102 brtc .-102 brid .-102
F67x brcc .-100 brne .-100 brpl .-100 brvc .-100 brge .-100 brhc .-100 brtc .-100 brid .-100 brcc .-98 brne .-98 brpl .-98 brvc .-98 brge .-98 brhc .-98 brtc .-98 brid .-98
F68x brcc .-96 brne .-96 brpl .-96 brvc .-96 brge .-96 brhc .-96 brtc .-96 brid .-96 brcc .-94 brne .-94 brpl .-94 brvc .-94 brge .-94 brhc .-94 brtc .-94 brid .-94
F69x brcc .-92 brne .-92 brpl .-92 brvc .-92 brge .-92 brhc .-92 brtc .-92 brid .-92 brcc .-90 brne .-90 brpl .-90 brvc .-90 brge .-90 brhc .-90 brtc .-90 brid .-90
F6Ax brcc .-88 brne .-88 brpl .-88 brvc .-88 brge .-88 brhc .-88 brtc .-88 brid .-88 brcc .-86 brne .-86 brpl .-86 brvc .-86 brge .-86 brhc .-86 brtc .-86 brid .-86
F6Bx brcc .-84 brne .-84 brpl .-84 brvc .-84 brge .-84 brhc .-84 brtc .-84 brid .-84 brcc .-82 brne .-82 brpl .-82 brvc .-82 brge .-82 brhc .-82 brtc .-82 brid .-82
F6Cx brcc .-80 brne .-80 brpl .-80 brvc .-80 brge .-80 brhc .-80 brtc .-80 brid .-80 brcc .-78 brne .-78 brpl .-78 brvc .-78 brge .-78 brhc .-78 brtc .-78 brid .-78
F6Dx brcc .-76 brne .-76 brpl .-76 brvc .-76 brge .-76 brhc .-76 brtc .-76 brid .-76 brcc .-74 brne .-74 brpl .-74 brvc .-74 brge .-74 brhc .-74 brtc .-74 brid .-74
F6Ex brcc .-72 brne .-72 brpl .-72 brvc .-72 brge .-72 brhc .-72 brtc .-72 brid .-72 brcc .-70 brne .-70 brpl .-70 brvc .-70 brge .-70 brhc .-70 brtc .-70 brid .-70
F6Fx brcc .-68 brne .-68 brpl .-68 brvc .-68 brge .-68 brhc .-68 brtc .-68 brid .-68 brcc .-66 brne .-66 brpl .-66 brvc .-66 brge .-66 brhc .-66 brtc .-66 brid .-66
brcc - BRanch if Carry Clear
brge - BRanch if Greater or Equal (signed)
brhc - BRanch if Half-carry Clear
brid - BRanch if global Interrupt flag disabled
brne - BRanch if Not Equal (Z flag clear)
brpl - BRanch if PLus (N flag clear)
brtc - BRanch if T flag Clear in SREG
brvc - BRanch if oVerflow flag Clear in SREG
^ summary

Opcodes F7xx (0xF700 - 0xF7FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F70x brcc .-64 brne .-64 brpl .-64 brvc .-64 brge .-64 brhc .-64 brtc .-64 brid .-64 brcc .-62 brne .-62 brpl .-62 brvc .-62 brge .-62 brhc .-62 brtc .-62 brid .-62
F71x brcc .-60 brne .-60 brpl .-60 brvc .-60 brge .-60 brhc .-60 brtc .-60 brid .-60 brcc .-58 brne .-58 brpl .-58 brvc .-58 brge .-58 brhc .-58 brtc .-58 brid .-58
F72x brcc .-56 brne .-56 brpl .-56 brvc .-56 brge .-56 brhc .-56 brtc .-56 brid .-56 brcc .-54 brne .-54 brpl .-54 brvc .-54 brge .-54 brhc .-54 brtc .-54 brid .-54
F73x brcc .-52 brne .-52 brpl .-52 brvc .-52 brge .-52 brhc .-52 brtc .-52 brid .-52 brcc .-50 brne .-50 brpl .-50 brvc .-50 brge .-50 brhc .-50 brtc .-50 brid .-50
F74x brcc .-48 brne .-48 brpl .-48 brvc .-48 brge .-48 brhc .-48 brtc .-48 brid .-48 brcc .-46 brne .-46 brpl .-46 brvc .-46 brge .-46 brhc .-46 brtc .-46 brid .-46
F75x brcc .-44 brne .-44 brpl .-44 brvc .-44 brge .-44 brhc .-44 brtc .-44 brid .-44 brcc .-42 brne .-42 brpl .-42 brvc .-42 brge .-42 brhc .-42 brtc .-42 brid .-42
F76x brcc .-40 brne .-40 brpl .-40 brvc .-40 brge .-40 brhc .-40 brtc .-40 brid .-40 brcc .-38 brne .-38 brpl .-38 brvc .-38 brge .-38 brhc .-38 brtc .-38 brid .-38
F77x brcc .-36 brne .-36 brpl .-36 brvc .-36 brge .-36 brhc .-36 brtc .-36 brid .-36 brcc .-34 brne .-34 brpl .-34 brvc .-34 brge .-34 brhc .-34 brtc .-34 brid .-34
F78x brcc .-32 brne .-32 brpl .-32 brvc .-32 brge .-32 brhc .-32 brtc .-32 brid .-32 brcc .-30 brne .-30 brpl .-30 brvc .-30 brge .-30 brhc .-30 brtc .-30 brid .-30
F79x brcc .-28 brne .-28 brpl .-28 brvc .-28 brge .-28 brhc .-28 brtc .-28 brid .-28 brcc .-26 brne .-26 brpl .-26 brvc .-26 brge .-26 brhc .-26 brtc .-26 brid .-26
F7Ax brcc .-24 brne .-24 brpl .-24 brvc .-24 brge .-24 brhc .-24 brtc .-24 brid .-24 brcc .-22 brne .-22 brpl .-22 brvc .-22 brge .-22 brhc .-22 brtc .-22 brid .-22
F7Bx brcc .-20 brne .-20 brpl .-20 brvc .-20 brge .-20 brhc .-20 brtc .-20 brid .-20 brcc .-18 brne .-18 brpl .-18 brvc .-18 brge .-18 brhc .-18 brtc .-18 brid .-18
F7Cx brcc .-16 brne .-16 brpl .-16 brvc .-16 brge .-16 brhc .-16 brtc .-16 brid .-16 brcc .-14 brne .-14 brpl .-14 brvc .-14 brge .-14 brhc .-14 brtc .-14 brid .-14
F7Dx brcc .-12 brne .-12 brpl .-12 brvc .-12 brge .-12 brhc .-12 brtc .-12 brid .-12 brcc .-10 brne .-10 brpl .-10 brvc .-10 brge .-10 brhc .-10 brtc .-10 brid .-10
F7Ex brcc .-8 brne .-8 brpl .-8 brvc .-8 brge .-8 brhc .-8 brtc .-8 brid .-8 brcc .-6 brne .-6 brpl .-6 brvc .-6 brge .-6 brhc .-6 brtc .-6 brid .-6
F7Fx brcc .-4 brne .-4 brpl .-4 brvc .-4 brge .-4 brhc .-4 brtc .-4 brid .-4 brcc .-2 brne .-2 brpl .-2 brvc .-2 brge .-2 brhc .-2 brtc .-2 brid .-2
brcc - BRanch if Carry Clear
brge - BRanch if Greater or Equal (signed)
brhc - BRanch if Half-carry Clear
brid - BRanch if global Interrupt flag disabled
brne - BRanch if Not Equal (Z flag clear)
brpl - BRanch if PLus (N flag clear)
brtc - BRanch if T flag Clear in SREG
brvc - BRanch if oVerflow flag Clear in SREG
^ summary

Opcodes F8xx (0xF800 - 0xF8FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F80x bld r0, 0 bld r0, 1 bld r0, 2 bld r0, 3 bld r0, 4 bld r0, 5 bld r0, 6 bld r0, 7 [R]
F81x bld r1, 0 bld r1, 1 bld r1, 2 bld r1, 3 bld r1, 4 bld r1, 5 bld r1, 6 bld r1, 7 [R]
F82x bld r2, 0 bld r2, 1 bld r2, 2 bld r2, 3 bld r2, 4 bld r2, 5 bld r2, 6 bld r2, 7 [R]
F83x bld r3, 0 bld r3, 1 bld r3, 2 bld r3, 3 bld r3, 4 bld r3, 5 bld r3, 6 bld r3, 7 [R]
F84x bld r4, 0 bld r4, 1 bld r4, 2 bld r4, 3 bld r4, 4 bld r4, 5 bld r4, 6 bld r4, 7 [R]
F85x bld r5, 0 bld r5, 1 bld r5, 2 bld r5, 3 bld r5, 4 bld r5, 5 bld r5, 6 bld r5, 7 [R]
F86x bld r6, 0 bld r6, 1 bld r6, 2 bld r6, 3 bld r6, 4 bld r6, 5 bld r6, 6 bld r6, 7 [R]
F87x bld r7, 0 bld r7, 1 bld r7, 2 bld r7, 3 bld r7, 4 bld r7, 5 bld r7, 6 bld r7, 7 [R]
F88x bld r8, 0 bld r8, 1 bld r8, 2 bld r8, 3 bld r8, 4 bld r8, 5 bld r8, 6 bld r8, 7 [R]
F89x bld r9, 0 bld r9, 1 bld r9, 2 bld r9, 3 bld r9, 4 bld r9, 5 bld r9, 6 bld r9, 7 [R]
F8Ax bld r10, 0 bld r10, 1 bld r10, 2 bld r10, 3 bld r10, 4 bld r10, 5 bld r10, 6 bld r10, 7 [R]
F8Bx bld r11, 0 bld r11, 1 bld r11, 2 bld r11, 3 bld r11, 4 bld r11, 5 bld r11, 6 bld r11, 7 [R]
F8Cx bld r12, 0 bld r12, 1 bld r12, 2 bld r12, 3 bld r12, 4 bld r12, 5 bld r12, 6 bld r12, 7 [R]
F8Dx bld r13, 0 bld r13, 1 bld r13, 2 bld r13, 3 bld r13, 4 bld r13, 5 bld r13, 6 bld r13, 7 [R]
F8Ex bld r14, 0 bld r14, 1 bld r14, 2 bld r14, 3 bld r14, 4 bld r14, 5 bld r14, 6 bld r14, 7 [R]
F8Fx bld r15, 0 bld r15, 1 bld r15, 2 bld r15, 3 bld r15, 4 bld r15, 5 bld r15, 6 bld r15, 7 [R]

[R] = Reserved (128)

bld - Bit LoaD from T in SREG to the specified bit of the register
^ summary

Opcodes F9xx (0xF900 - 0xF9FF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
F90x bld r16, 0 bld r16, 1 bld r16, 2 bld r16, 3 bld r16, 4 bld r16, 5 bld r16, 6 bld r16, 7 [R]
F91x bld r17, 0 bld r17, 1 bld r17, 2 bld r17, 3 bld r17, 4 bld r17, 5 bld r17, 6 bld r17, 7 [R]
F92x bld r18, 0 bld r18, 1 bld r18, 2 bld r18, 3 bld r18, 4 bld r18, 5 bld r18, 6 bld r18, 7 [R]
F93x bld r19, 0 bld r19, 1 bld r19, 2 bld r19, 3 bld r19, 4 bld r19, 5 bld r19, 6 bld r19, 7 [R]
F94x bld r20, 0 bld r20, 1 bld r20, 2 bld r20, 3 bld r20, 4 bld r20, 5 bld r20, 6 bld r20, 7 [R]
F95x bld r21, 0 bld r21, 1 bld r21, 2 bld r21, 3 bld r21, 4 bld r21, 5 bld r21, 6 bld r21, 7 [R]
F96x bld r22, 0 bld r22, 1 bld r22, 2 bld r22, 3 bld r22, 4 bld r22, 5 bld r22, 6 bld r22, 7 [R]
F97x bld r23, 0 bld r23, 1 bld r23, 2 bld r23, 3 bld r23, 4 bld r23, 5 bld r23, 6 bld r23, 7 [R]
F98x bld r24, 0 bld r24, 1 bld r24, 2 bld r24, 3 bld r24, 4 bld r24, 5 bld r24, 6 bld r24, 7 [R]
F99x bld r25, 0 bld r25, 1 bld r25, 2 bld r25, 3 bld r25, 4 bld r25, 5 bld r25, 6 bld r25, 7 [R]
F9Ax bld r26, 0 bld r26, 1 bld r26, 2 bld r26, 3 bld r26, 4 bld r26, 5 bld r26, 6 bld r26, 7 [R]
F9Bx bld r27, 0 bld r27, 1 bld r27, 2 bld r27, 3 bld r27, 4 bld r27, 5 bld r27, 6 bld r27, 7 [R]
F9Cx bld r28, 0 bld r28, 1 bld r28, 2 bld r28, 3 bld r28, 4 bld r28, 5 bld r28, 6 bld r28, 7 [R]
F9Dx bld r29, 0 bld r29, 1 bld r29, 2 bld r29, 3 bld r29, 4 bld r29, 5 bld r29, 6 bld r29, 7 [R]
F9Ex bld r30, 0 bld r30, 1 bld r30, 2 bld r30, 3 bld r30, 4 bld r30, 5 bld r30, 6 bld r30, 7 [R]
F9Fx bld r31, 0 bld r31, 1 bld r31, 2 bld r31, 3 bld r31, 4 bld r31, 5 bld r31, 6 bld r31, 7 [R]

[R] = Reserved (128)

bld - Bit LoaD from T in SREG to the specified bit of the register
^ summary

Opcodes FAxx (0xFA00 - 0xFAFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FA0x bst r0, 0 bst r0, 1 bst r0, 2 bst r0, 3 bst r0, 4 bst r0, 5 bst r0, 6 bst r0, 7 [R]
FA1x bst r1, 0 bst r1, 1 bst r1, 2 bst r1, 3 bst r1, 4 bst r1, 5 bst r1, 6 bst r1, 7 [R]
FA2x bst r2, 0 bst r2, 1 bst r2, 2 bst r2, 3 bst r2, 4 bst r2, 5 bst r2, 6 bst r2, 7 [R]
FA3x bst r3, 0 bst r3, 1 bst r3, 2 bst r3, 3 bst r3, 4 bst r3, 5 bst r3, 6 bst r3, 7 [R]
FA4x bst r4, 0 bst r4, 1 bst r4, 2 bst r4, 3 bst r4, 4 bst r4, 5 bst r4, 6 bst r4, 7 [R]
FA5x bst r5, 0 bst r5, 1 bst r5, 2 bst r5, 3 bst r5, 4 bst r5, 5 bst r5, 6 bst r5, 7 [R]
FA6x bst r6, 0 bst r6, 1 bst r6, 2 bst r6, 3 bst r6, 4 bst r6, 5 bst r6, 6 bst r6, 7 [R]
FA7x bst r7, 0 bst r7, 1 bst r7, 2 bst r7, 3 bst r7, 4 bst r7, 5 bst r7, 6 bst r7, 7 [R]
FA8x bst r8, 0 bst r8, 1 bst r8, 2 bst r8, 3 bst r8, 4 bst r8, 5 bst r8, 6 bst r8, 7 [R]
FA9x bst r9, 0 bst r9, 1 bst r9, 2 bst r9, 3 bst r9, 4 bst r9, 5 bst r9, 6 bst r9, 7 [R]
FAAx bst r10, 0 bst r10, 1 bst r10, 2 bst r10, 3 bst r10, 4 bst r10, 5 bst r10, 6 bst r10, 7 [R]
FABx bst r11, 0 bst r11, 1 bst r11, 2 bst r11, 3 bst r11, 4 bst r11, 5 bst r11, 6 bst r11, 7 [R]
FACx bst r12, 0 bst r12, 1 bst r12, 2 bst r12, 3 bst r12, 4 bst r12, 5 bst r12, 6 bst r12, 7 [R]
FADx bst r13, 0 bst r13, 1 bst r13, 2 bst r13, 3 bst r13, 4 bst r13, 5 bst r13, 6 bst r13, 7 [R]
FAEx bst r14, 0 bst r14, 1 bst r14, 2 bst r14, 3 bst r14, 4 bst r14, 5 bst r14, 6 bst r14, 7 [R]
FAFx bst r15, 0 bst r15, 1 bst r15, 2 bst r15, 3 bst r15, 4 bst r15, 5 bst r15, 6 bst r15, 7 [R]

[R] = Reserved (128)

bst - Bit STore from the specified bit in the register
^ summary

Opcodes FBxx (0xFB00 - 0xFBFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FB0x bst r16, 0 bst r16, 1 bst r16, 2 bst r16, 3 bst r16, 4 bst r16, 5 bst r16, 6 bst r16, 7 [R]
FB1x bst r17, 0 bst r17, 1 bst r17, 2 bst r17, 3 bst r17, 4 bst r17, 5 bst r17, 6 bst r17, 7 [R]
FB2x bst r18, 0 bst r18, 1 bst r18, 2 bst r18, 3 bst r18, 4 bst r18, 5 bst r18, 6 bst r18, 7 [R]
FB3x bst r19, 0 bst r19, 1 bst r19, 2 bst r19, 3 bst r19, 4 bst r19, 5 bst r19, 6 bst r19, 7 [R]
FB4x bst r20, 0 bst r20, 1 bst r20, 2 bst r20, 3 bst r20, 4 bst r20, 5 bst r20, 6 bst r20, 7 [R]
FB5x bst r21, 0 bst r21, 1 bst r21, 2 bst r21, 3 bst r21, 4 bst r21, 5 bst r21, 6 bst r21, 7 [R]
FB6x bst r22, 0 bst r22, 1 bst r22, 2 bst r22, 3 bst r22, 4 bst r22, 5 bst r22, 6 bst r22, 7 [R]
FB7x bst r23, 0 bst r23, 1 bst r23, 2 bst r23, 3 bst r23, 4 bst r23, 5 bst r23, 6 bst r23, 7 [R]
FB8x bst r24, 0 bst r24, 1 bst r24, 2 bst r24, 3 bst r24, 4 bst r24, 5 bst r24, 6 bst r24, 7 [R]
FB9x bst r25, 0 bst r25, 1 bst r25, 2 bst r25, 3 bst r25, 4 bst r25, 5 bst r25, 6 bst r25, 7 [R]
FBAx bst r26, 0 bst r26, 1 bst r26, 2 bst r26, 3 bst r26, 4 bst r26, 5 bst r26, 6 bst r26, 7 [R]
FBBx bst r27, 0 bst r27, 1 bst r27, 2 bst r27, 3 bst r27, 4 bst r27, 5 bst r27, 6 bst r27, 7 [R]
FBCx bst r28, 0 bst r28, 1 bst r28, 2 bst r28, 3 bst r28, 4 bst r28, 5 bst r28, 6 bst r28, 7 [R]
FBDx bst r29, 0 bst r29, 1 bst r29, 2 bst r29, 3 bst r29, 4 bst r29, 5 bst r29, 6 bst r29, 7 [R]
FBEx bst r30, 0 bst r30, 1 bst r30, 2 bst r30, 3 bst r30, 4 bst r30, 5 bst r30, 6 bst r30, 7 [R]
FBFx bst r31, 0 bst r31, 1 bst r31, 2 bst r31, 3 bst r31, 4 bst r31, 5 bst r31, 6 bst r31, 7 [R]

[R] = Reserved (128)

bst - Bit STore from the specified bit in the register
^ summary

Opcodes FCxx (0xFC00 - 0xFCFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FC0x sbrc r0, 0 sbrc r0, 1 sbrc r0, 2 sbrc r0, 3 sbrc r0, 4 sbrc r0, 5 sbrc r0, 6 sbrc r0, 7 [R]
FC1x sbrc r1, 0 sbrc r1, 1 sbrc r1, 2 sbrc r1, 3 sbrc r1, 4 sbrc r1, 5 sbrc r1, 6 sbrc r1, 7 [R]
FC2x sbrc r2, 0 sbrc r2, 1 sbrc r2, 2 sbrc r2, 3 sbrc r2, 4 sbrc r2, 5 sbrc r2, 6 sbrc r2, 7 [R]
FC3x sbrc r3, 0 sbrc r3, 1 sbrc r3, 2 sbrc r3, 3 sbrc r3, 4 sbrc r3, 5 sbrc r3, 6 sbrc r3, 7 [R]
FC4x sbrc r4, 0 sbrc r4, 1 sbrc r4, 2 sbrc r4, 3 sbrc r4, 4 sbrc r4, 5 sbrc r4, 6 sbrc r4, 7 [R]
FC5x sbrc r5, 0 sbrc r5, 1 sbrc r5, 2 sbrc r5, 3 sbrc r5, 4 sbrc r5, 5 sbrc r5, 6 sbrc r5, 7 [R]
FC6x sbrc r6, 0 sbrc r6, 1 sbrc r6, 2 sbrc r6, 3 sbrc r6, 4 sbrc r6, 5 sbrc r6, 6 sbrc r6, 7 [R]
FC7x sbrc r7, 0 sbrc r7, 1 sbrc r7, 2 sbrc r7, 3 sbrc r7, 4 sbrc r7, 5 sbrc r7, 6 sbrc r7, 7 [R]
FC8x sbrc r8, 0 sbrc r8, 1 sbrc r8, 2 sbrc r8, 3 sbrc r8, 4 sbrc r8, 5 sbrc r8, 6 sbrc r8, 7 [R]
FC9x sbrc r9, 0 sbrc r9, 1 sbrc r9, 2 sbrc r9, 3 sbrc r9, 4 sbrc r9, 5 sbrc r9, 6 sbrc r9, 7 [R]
FCAx sbrc r10, 0 sbrc r10, 1 sbrc r10, 2 sbrc r10, 3 sbrc r10, 4 sbrc r10, 5 sbrc r10, 6 sbrc r10, 7 [R]
FCBx sbrc r11, 0 sbrc r11, 1 sbrc r11, 2 sbrc r11, 3 sbrc r11, 4 sbrc r11, 5 sbrc r11, 6 sbrc r11, 7 [R]
FCCx sbrc r12, 0 sbrc r12, 1 sbrc r12, 2 sbrc r12, 3 sbrc r12, 4 sbrc r12, 5 sbrc r12, 6 sbrc r12, 7 [R]
FCDx sbrc r13, 0 sbrc r13, 1 sbrc r13, 2 sbrc r13, 3 sbrc r13, 4 sbrc r13, 5 sbrc r13, 6 sbrc r13, 7 [R]
FCEx sbrc r14, 0 sbrc r14, 1 sbrc r14, 2 sbrc r14, 3 sbrc r14, 4 sbrc r14, 5 sbrc r14, 6 sbrc r14, 7 [R]
FCFx sbrc r15, 0 sbrc r15, 1 sbrc r15, 2 sbrc r15, 3 sbrc r15, 4 sbrc r15, 5 sbrc r15, 6 sbrc r15, 7 [R]

[R] = Reserved (128)

sbrc - Skip next instruction if Bit in Register is Clear
^ summary

Opcodes FDxx (0xFD00 - 0xFDFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FD0x sbrc r16, 0 sbrc r16, 1 sbrc r16, 2 sbrc r16, 3 sbrc r16, 4 sbrc r16, 5 sbrc r16, 6 sbrc r16, 7 [R]
FD1x sbrc r17, 0 sbrc r17, 1 sbrc r17, 2 sbrc r17, 3 sbrc r17, 4 sbrc r17, 5 sbrc r17, 6 sbrc r17, 7 [R]
FD2x sbrc r18, 0 sbrc r18, 1 sbrc r18, 2 sbrc r18, 3 sbrc r18, 4 sbrc r18, 5 sbrc r18, 6 sbrc r18, 7 [R]
FD3x sbrc r19, 0 sbrc r19, 1 sbrc r19, 2 sbrc r19, 3 sbrc r19, 4 sbrc r19, 5 sbrc r19, 6 sbrc r19, 7 [R]
FD4x sbrc r20, 0 sbrc r20, 1 sbrc r20, 2 sbrc r20, 3 sbrc r20, 4 sbrc r20, 5 sbrc r20, 6 sbrc r20, 7 [R]
FD5x sbrc r21, 0 sbrc r21, 1 sbrc r21, 2 sbrc r21, 3 sbrc r21, 4 sbrc r21, 5 sbrc r21, 6 sbrc r21, 7 [R]
FD6x sbrc r22, 0 sbrc r22, 1 sbrc r22, 2 sbrc r22, 3 sbrc r22, 4 sbrc r22, 5 sbrc r22, 6 sbrc r22, 7 [R]
FD7x sbrc r23, 0 sbrc r23, 1 sbrc r23, 2 sbrc r23, 3 sbrc r23, 4 sbrc r23, 5 sbrc r23, 6 sbrc r23, 7 [R]
FD8x sbrc r24, 0 sbrc r24, 1 sbrc r24, 2 sbrc r24, 3 sbrc r24, 4 sbrc r24, 5 sbrc r24, 6 sbrc r24, 7 [R]
FD9x sbrc r25, 0 sbrc r25, 1 sbrc r25, 2 sbrc r25, 3 sbrc r25, 4 sbrc r25, 5 sbrc r25, 6 sbrc r25, 7 [R]
FDAx sbrc r26, 0 sbrc r26, 1 sbrc r26, 2 sbrc r26, 3 sbrc r26, 4 sbrc r26, 5 sbrc r26, 6 sbrc r26, 7 [R]
FDBx sbrc r27, 0 sbrc r27, 1 sbrc r27, 2 sbrc r27, 3 sbrc r27, 4 sbrc r27, 5 sbrc r27, 6 sbrc r27, 7 [R]
FDCx sbrc r28, 0 sbrc r28, 1 sbrc r28, 2 sbrc r28, 3 sbrc r28, 4 sbrc r28, 5 sbrc r28, 6 sbrc r28, 7 [R]
FDDx sbrc r29, 0 sbrc r29, 1 sbrc r29, 2 sbrc r29, 3 sbrc r29, 4 sbrc r29, 5 sbrc r29, 6 sbrc r29, 7 [R]
FDEx sbrc r30, 0 sbrc r30, 1 sbrc r30, 2 sbrc r30, 3 sbrc r30, 4 sbrc r30, 5 sbrc r30, 6 sbrc r30, 7 [R]
FDFx sbrc r31, 0 sbrc r31, 1 sbrc r31, 2 sbrc r31, 3 sbrc r31, 4 sbrc r31, 5 sbrc r31, 6 sbrc r31, 7 [R]

[R] = Reserved (128)

sbrc - Skip next instruction if Bit in Register is Clear
^ summary

Opcodes FExx (0xFE00 - 0xFEFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FE0x sbrs r0, 0 sbrs r0, 1 sbrs r0, 2 sbrs r0, 3 sbrs r0, 4 sbrs r0, 5 sbrs r0, 6 sbrs r0, 7 [R]
FE1x sbrs r1, 0 sbrs r1, 1 sbrs r1, 2 sbrs r1, 3 sbrs r1, 4 sbrs r1, 5 sbrs r1, 6 sbrs r1, 7 [R]
FE2x sbrs r2, 0 sbrs r2, 1 sbrs r2, 2 sbrs r2, 3 sbrs r2, 4 sbrs r2, 5 sbrs r2, 6 sbrs r2, 7 [R]
FE3x sbrs r3, 0 sbrs r3, 1 sbrs r3, 2 sbrs r3, 3 sbrs r3, 4 sbrs r3, 5 sbrs r3, 6 sbrs r3, 7 [R]
FE4x sbrs r4, 0 sbrs r4, 1 sbrs r4, 2 sbrs r4, 3 sbrs r4, 4 sbrs r4, 5 sbrs r4, 6 sbrs r4, 7 [R]
FE5x sbrs r5, 0 sbrs r5, 1 sbrs r5, 2 sbrs r5, 3 sbrs r5, 4 sbrs r5, 5 sbrs r5, 6 sbrs r5, 7 [R]
FE6x sbrs r6, 0 sbrs r6, 1 sbrs r6, 2 sbrs r6, 3 sbrs r6, 4 sbrs r6, 5 sbrs r6, 6 sbrs r6, 7 [R]
FE7x sbrs r7, 0 sbrs r7, 1 sbrs r7, 2 sbrs r7, 3 sbrs r7, 4 sbrs r7, 5 sbrs r7, 6 sbrs r7, 7 [R]
FE8x sbrs r8, 0 sbrs r8, 1 sbrs r8, 2 sbrs r8, 3 sbrs r8, 4 sbrs r8, 5 sbrs r8, 6 sbrs r8, 7 [R]
FE9x sbrs r9, 0 sbrs r9, 1 sbrs r9, 2 sbrs r9, 3 sbrs r9, 4 sbrs r9, 5 sbrs r9, 6 sbrs r9, 7 [R]
FEAx sbrs r10, 0 sbrs r10, 1 sbrs r10, 2 sbrs r10, 3 sbrs r10, 4 sbrs r10, 5 sbrs r10, 6 sbrs r10, 7 [R]
FEBx sbrs r11, 0 sbrs r11, 1 sbrs r11, 2 sbrs r11, 3 sbrs r11, 4 sbrs r11, 5 sbrs r11, 6 sbrs r11, 7 [R]
FECx sbrs r12, 0 sbrs r12, 1 sbrs r12, 2 sbrs r12, 3 sbrs r12, 4 sbrs r12, 5 sbrs r12, 6 sbrs r12, 7 [R]
FEDx sbrs r13, 0 sbrs r13, 1 sbrs r13, 2 sbrs r13, 3 sbrs r13, 4 sbrs r13, 5 sbrs r13, 6 sbrs r13, 7 [R]
FEEx sbrs r14, 0 sbrs r14, 1 sbrs r14, 2 sbrs r14, 3 sbrs r14, 4 sbrs r14, 5 sbrs r14, 6 sbrs r14, 7 [R]
FEFx sbrs r15, 0 sbrs r15, 1 sbrs r15, 2 sbrs r15, 3 sbrs r15, 4 sbrs r15, 5 sbrs r15, 6 sbrs r15, 7 [R]

[R] = Reserved (128)

sbrs - Skip next instruction if Bit in Register is Set
^ summary

Opcodes FFxx (0xFF00 - 0xFFFF)

0 1 2 3 4 5 6 7 8 9 A B C D E F
FF0x sbrs r16, 0 sbrs r16, 1 sbrs r16, 2 sbrs r16, 3 sbrs r16, 4 sbrs r16, 5 sbrs r16, 6 sbrs r16, 7 [R]
FF1x sbrs r17, 0 sbrs r17, 1 sbrs r17, 2 sbrs r17, 3 sbrs r17, 4 sbrs r17, 5 sbrs r17, 6 sbrs r17, 7 [R]
FF2x sbrs r18, 0 sbrs r18, 1 sbrs r18, 2 sbrs r18, 3 sbrs r18, 4 sbrs r18, 5 sbrs r18, 6 sbrs r18, 7 [R]
FF3x sbrs r19, 0 sbrs r19, 1 sbrs r19, 2 sbrs r19, 3 sbrs r19, 4 sbrs r19, 5 sbrs r19, 6 sbrs r19, 7 [R]
FF4x sbrs r20, 0 sbrs r20, 1 sbrs r20, 2 sbrs r20, 3 sbrs r20, 4 sbrs r20, 5 sbrs r20, 6 sbrs r20, 7 [R]
FF5x sbrs r21, 0 sbrs r21, 1 sbrs r21, 2 sbrs r21, 3 sbrs r21, 4 sbrs r21, 5 sbrs r21, 6 sbrs r21, 7 [R]
FF6x sbrs r22, 0 sbrs r22, 1 sbrs r22, 2 sbrs r22, 3 sbrs r22, 4 sbrs r22, 5 sbrs r22, 6 sbrs r22, 7 [R]
FF7x sbrs r23, 0 sbrs r23, 1 sbrs r23, 2 sbrs r23, 3 sbrs r23, 4 sbrs r23, 5 sbrs r23, 6 sbrs r23, 7 [R]
FF8x sbrs r24, 0 sbrs r24, 1 sbrs r24, 2 sbrs r24, 3 sbrs r24, 4 sbrs r24, 5 sbrs r24, 6 sbrs r24, 7 [R]
FF9x sbrs r25, 0 sbrs r25, 1 sbrs r25, 2 sbrs r25, 3 sbrs r25, 4 sbrs r25, 5 sbrs r25, 6 sbrs r25, 7 [R]
FFAx sbrs r26, 0 sbrs r26, 1 sbrs r26, 2 sbrs r26, 3 sbrs r26, 4 sbrs r26, 5 sbrs r26, 6 sbrs r26, 7 [R]
FFBx sbrs r27, 0 sbrs r27, 1 sbrs r27, 2 sbrs r27, 3 sbrs r27, 4 sbrs r27, 5 sbrs r27, 6 sbrs r27, 7 [R]
FFCx sbrs r28, 0 sbrs r28, 1 sbrs r28, 2 sbrs r28, 3 sbrs r28, 4 sbrs r28, 5 sbrs r28, 6 sbrs r28, 7 [R]
FFDx sbrs r29, 0 sbrs r29, 1 sbrs r29, 2 sbrs r29, 3 sbrs r29, 4 sbrs r29, 5 sbrs r29, 6 sbrs r29, 7 [R]
FFEx sbrs r30, 0 sbrs r30, 1 sbrs r30, 2 sbrs r30, 3 sbrs r30, 4 sbrs r30, 5 sbrs r30, 6 sbrs r30, 7 [R]
FFFx sbrs r31, 0 sbrs r31, 1 sbrs r31, 2 sbrs r31, 3 sbrs r31, 4 sbrs r31, 5 sbrs r31, 6 sbrs r31, 7 [R]

[R] = Reserved (128)

sbrs - Skip next instruction if Bit in Register is Set
^ summary

Generated from avr-objdump version 'GNU objdump 2.17 + coff-avr-patch (20050630) '